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PDF V54C365164 Data sheet ( Hoja de datos )
| Número de pieza | V54C365164 | |
| Descripción | HIGH PERFORMANCE 166/143/125 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 | |
| Fabricantes | Mosel Vitelic Corp | |
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MOSEL VITELIC
V54C365164VC
HIGH PERFORMANCE 166/143/125 MHz
3.3 VOLT 4M X 16 SYNCHRONOUS DRAM
4 BANKS X 1Mbit X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
6
166 MHz
6 ns
5.4 ns
5.5 ns
13 ns
7
143 MHz
7 ns
5.4 ns
5.5 ns
13 ns
8PC
125 MHz
8 ns
6 ns
6 ns
13 ns
Features
I 4 banks x 1Mbit x 16 organization
I High speed data transfer rates up to 166 MHz
I Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I Single Pulsed RAS Interface
I Data Mask for byte Control
I Four Banks controlled by BA0 & BA1
I Programmable CAS Latency: 1, 2, & 3
I Programmable Wrap Sequence: Sequential or
Interleave
I Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
I Multiple Burst Read with Single Write Operation
I Automatic and Controlled Precharge Command
I Random Column Address every CLK (1-N Rule)
I Suspend Mode and Power Down Mode
I Auto Refresh and Self Refresh
I Refresh Interval: 4096 cycles/64 ms
I Available in 54 Pin 400 mil TSOP-II
I LVTTL Interface
I Single +3.3 V ±0.3 V Power Supply
Description
The V54C365164VC is a four bank Synchronous
DRAM organized as 4 banks x 1Mbit x 16. The
V54C365164VC achieves high speed data transfer
rates up to 166 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
•
Access Time (ns)
6 7 8PC
••
•
Power
Std. L
••
Temperature
Mark
Blank
V54C365164VC Rev. 0.8 July 2001
1
1 page  
MOSEL VITELIC
V54C365164VC
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable
Device CKE CKE
A0-9,
BS0
State n-1 n CS RAS CAS WE DQM A11 A10 BS1
Idle3 H X L L H H X V V V
Active3
H
X
L
HLHX
V
L
V
Active3
H
X
L
H
L
H
X
V
H
V
Active3
H
X
L
HL
L
X
V
L
V
Active3
H
X
L
H
L
L
X
V
H
V
Any H X L L H L X X L V
Any H X L L H L X X H X
Idle H X L L L L X V V V
Any H X L H H H X X X X
Any H X H X X X X X X X
Idle H H L L L H X X X X
Idle H L L L L H X X X X
Idle H X X X
(Self Refr.) L
H
XXX X
L HHX
Idle H X X X
Active5
H
L
XXX X
L HHX
Any H X X X
(Power
L
H
XXX X
Down)
L HH L
Active
H
X
X
X
X
X
L
X
X
X
Active
H
X
X
X
X
X
H
X
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.
V54C365164VC Rev. 0.8 July 2001
5
5 Page 
MOSEL VITELIC
Operating Currents (TA = 0 to 70°C, VCC = 3.3V ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Symbol Parameter & Test Condition
ICC1
Operating Current
tRC = tRCMIN., tRC = tCKMIN.
Active-precharge command
cycling,
without Burst Operation
ICC2P
ICC2PS
Precharge Standby Current
in Power Down Mode
CS =VIH, CKE≤ VIL(max)
ICC2N
ICC2NS
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
1 bank operation
tCK = min.
tCK = Infinity
tCK = min.
tCK = Infinity
V54C365164VC
Max.
-6 -7 -8PC Unit Note
165 150 130 mA 7
2 2 2 mA 7
1 1 1 mA 7
55 45 35 mA
5 5 5 mA
ICC3
ICC3P
No Operating Current
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE ≥ VIH(MIN.)
CKE ≥ VIL(MAX.)
(Power down mode)
65 55 45 mA
8 8 8 mA
ICC4
Burst Operating Current
tCK = min
Read/Write command cycling
130 120 110 mA 7,8
ICC5
Auto Refresh Current
tCK = min
Auto Refresh command cycling
165 150 130 mA 7
ICC6
Self Refresh Current
Self Refresh Mode, CKE=0.2V
L-version
1 1 1 mA
400 400 400 µA
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
8. These parameter depend on output loading. Specified values are obtained with output open.
V54C365164VC Rev. 0.8 July 2001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet V54C365164.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| V54C365164 | HIGH PERFORMANCE 166/143/125 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 | Mosel Vitelic Corp |
| V54C365164VC | HIGH PERFORMANCE 166/143/125 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 |  Mosel Vitelic Corp |
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