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PDF V54C3256404VT Data sheet ( Hoja de datos )

Número de pieza V54C3256404VT
Descripción 256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC BGA / WBGA
PACKAGE 16M X 16, 32M X 8, 64M X 4
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC BGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S/B
6
Access Time (ns)
7PC 7
••
8PC
Power
Std. L
••
Temperature
Mark
Blank
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
1

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V54C3256404VT pdf
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
Description Pkg.
TSOP-II
T
Pin Count
54
V 54 C 3 25640 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
3.3V, LVTTL INTERFACE
64Mx4(8K Refresh)
4 Banks
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
NC
VCCQ
NC
I/O1
VSSQ
NC
NC
VCCQ
NC
I/O2
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356404V-01
VSS
NC
VSSQ
NC
I/O4
VCCQ
NC
NC
VSSQ
NC
I/O3
VCCQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0–A12
BA0, BA1
I/O1–I/O4
DQM
VCC
VSS
VCCQ
VSSQ
NC
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
5

5 Page





V54C3256404VT arduino
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
Signal Pin Description
Pin Type
CLK Input
CKE
Input
CS Input
RAS, CAS Input
WE
A0 - A11 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
Edge clock.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Level
— During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 64M x 4 SDRAM CA0–CA9, CA11.
• 32M x 8 SDRAM CA0–CA9.
• 16M x 16 SDRAM CA0–CA8.
BA0,
BA1
DQx
LDQM
UDQM
Input
Input
Output
Input
VCC, VSS Supply
VCCQ
VSSQ
Supply
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
— Selects which bank is to be active.
Level
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
11

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