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PDF V54C316162 Data sheet ( Hoja de datos )

Número de pieza V54C316162
Descripción 200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
Fabricantes Mosel Vitelic Corp 
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No Preview Available ! V54C316162 Hoja de datos, Descripción, Manual

MOSEL VITELIC
V54C316162V
200/183/166/143 MHz 3.3 VOLT, 4K REFRESH
ULTRA HIGH PERFORMANCE
1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162V
Clock Frequency (tCK)
Latency
Cycle Time (tCK)
Access Time (tAC)
-5 -55 -6
-7 Unit
200 183 166 143 MHz
3 3 3 3 clocks
5 5.5 6
7 ns
5 5.3 5.5 5.5 ns
Features
s JEDEC Standard 3.3V Power Supply
s The V54C316162V is ideally suited for high per-
formance graphics peripheral applications
s Single Pulsed RAS Interface
s Programmable CAS Latency: 2, 3
s All Inputs are sampled at the positive going edge
of clock
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
s UDQM & LDQM for byte masking
s Auto & Self Refresh
s 4K Refresh Cycles/64 ms
s Burst Read with Single Write Operation
Description
The V54C316162V is a 16,777,216 bits synchro-
nous high data rate DRAM organized as 2 x
524,288 words by 16 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
V54C316162V Rev.2.9 September 2001
1

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V54C316162 pdf
MOSEL VITELIC
V54C316162V
Address Input for Mode Set (Mode Register Operation)
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)
Write Burst Length
Test
Mode
CAS Latency BT Burst Length Mode Register
Write Burst Length Test Mode
A9 Length
0 Burst
1 Single Bit
A8 A7 Mode
0
0
Mode Reg
Set
CAS Latency
A6 A5 A4
000
001
010
011
101
110
111
Latency
Reserve
Reserve
2
3
Reserve
Reserve
Reserve
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the NOPstate. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Burst Type
A3 Type
0 Sequential
1 Interleave
Burst Length
Length
A2 A1 A0
Sequential Interleave
000
1
1
001
2
2
010
4
4
011
8
8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Full Page Reserve
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst
cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Op-
eration mode field to differentiate between normal
operation (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set
operation. Address input data at this timing defines
parameters to be set as shown in the previous table.
V54C316162V Rev. 2.9 September 2001
5

5 Page





V54C316162 arduino
MOSEL VITELIC
V54C316162V
AC Characteristics (1,2,3) (Continued)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5 -55 -6
-7
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
24 tSREX Self Refresh Exit Time
Read Cycle
2 CLK + tRC
2 CLK + tRC
6
25 tOH
27 tHZ
Data Out Hold Time
CAS Latency = 3
CAS Latency = 2
2.5 2.5 2.5 2.5
ns
5 5.3 5.5 5.5 ns
7777
28 tDQZ
DQM Data Out Disable Latency
2
2
2
2
CLK
Write Cycle
29 tWR
Write Recovery Time
CAS Latency = 3
CAS Latency = 2
5 5.5 6 7 ns
10 10 10 10 ns
30 tDQW DQM Write Mask Latency
0 0 0 0 CLK
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1.
CLK
COMMAND
tCK
tCS tCH
1.4V
tAC
tLZ
VIH
VIL
tT
tAC
tOH
+ 1.4 V
50 Ohm
Z=50 Ohm
I/O
50 pF
OUTPUT
1.4V
tHZ
Figure 1.
3. If clock rising time is longer than 1 ns, a time (tT/2 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
V54C316162V Rev. 2.9 September 2001
11

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