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PDF V53C8125H Data sheet ( Hoja de datos )

Número de pieza V53C8125H
Descripción ULTRA-HIGH PERFORMANCE/ 128K X 8 FAST PAGE MODE CMOS DYNAMIC RAM
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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No Preview Available ! V53C8125H Hoja de datos, Descripción, Manual

MOSEL VITELIC
V53C8125H
ULTRA-HIGH PERFORMANCE,
128K X 8 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
30
30 ns
16 ns
19 ns
65 ns
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
Features
s 128K x 8-bit organization
s RAS access time: 30, 35, 40, 45, 50 ns
s Fast Page Mode supports sustained data rates
up to 53 MHz
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval: 256 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ and 28 pin
TSOP-I packages
Description
The V53C8125H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8125H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
columns (x9) bits within a row with cycle times as
short as 19 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8125H ideally suited for graphics,
digital signal processing and high performance pe-
ripherals.
Device Usage Chart
Operating
Package Outline
Access Time (ns)
Power
Temperature
Temperature
Range
K T 30 35 40 45 50 Std.
Mark
0°C to 70 °C
.
.
. . . .. .
Blank
V53C8125H Rev. 1.7 August 1998
1

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V53C8125H pdf
MOSEL VITELIC
V53C8125H
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
30 35 40 45 50
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
1 tRAS
2 tRC
3 tRP
4 tCSH
5 tCAS
6 tRCD
7 tRCS
8 tASR
9 tRAH
10 tASC
11 tCAH
12 tRSH (R)
13 tCRP
14 tRCH
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time (Read Cycle)
CAS to RAS Precharge Time
Read Command Hold Time
Referenced to CAS
30 75K 35 75K 40 75K 45 75K 50 75K ns
65 70 75 80 90 ns
25 25 25 25 30 ns
30 35 40 45 50 ns
5 6 7 8 9 ns
15 20 16 24 17 28 18 32 19 36 ns
0 0 0 0 0 ns
0 0 0 0 0 ns
5 6 7 8 9 ns
0 0 0 0 0 ns
5 5 5 6 7 ns
10 10 10 10 10 ns
5 5 5 5 5 ns
0 0 0 0 0 ns
4
5
15 tRRH
Read Command Hold Time
Referenced to RAS
0 0 0 0 0 ns
16 tROH
RAS Hold Time
Referenced to OE
6 7 8 9 10 ns
17 tOAC
18 tCAC
19 tRAC
20 tCAA
Access Time from OE
Access Time from CAS
Access Time from RAS
Access Time from Column
Address
10 11 12 13 14 ns 12
10 11 12 13 14 ns 6,7,14
30 35 40 45 50 ns 6, 8, 9
16 18 20 22 24 ns 6,7,10
21 tLZ
22 tHZ
23 tAR
OE or CAS to Low-Z Output
0
0
0
0
0 ns 16
OE or CAS to High-Z Output
0 5 0 6 0 6 0 7 0 8 ns 16
Column Address Hold Time from 26 28 30 35 40 ns
RAS
24 tRAD
RAS to Column Address
Delay Time
10 14 11 17 12 20 13 23 14 26 ns 11
25 tRSH (W) RAS or CAS Hold Time in
10
10
10
10
10
ns
Write Cycle
26 tCWL
Write Command to CAS
10
11
12
13
14
ns
Lead Time
27 tWCS
Write Command Setup Time
0
0
0
0
0 ns 12, 13
28 tWCH
Write Command Hold Time
5
5
5
6
7 ns
5
V53C8125H Rev. 1.7 August 1998
5

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V53C8125H arduino
MOSEL VITELIC
V53C8125H
Waveforms of Fast Page Mode Read-Write Cycle
RAS VIH
VIL
V
CAS IH
VIL
V
ADDRESS IH
VIL
V
WE
IH
VIL
V
OE IH
VIL
VI/OH
I/O
VI/OL
t RAS (1)
tRCD (6)
t CSH (4)
t PCM (50)
tRAD (24)
t CAS (5)
t RAH (9)
t ASC (10)
tASR (8)
t ASC (10)
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
tCP (43)
tCAS (5)
tRP (3)
tRSH (W)(25)
tCRP (13)
tCAS (5)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CAR (44)
t CAH (11)
COLUMN
ADDRESS
tRCS (7)
tRWD (39)
tCWD (38)
tCWD (38)
t CWL (26)
t CWL (26)
t CWD (38)
t RWL (31)
t CWL (26)
t CAA (20)
t OAC (17)
t AWD (41)
t AWD (41)
t WP (29)
t OAC (17)
t AWD (41)
tWP (29)
t OAC (17)
t WP (29)
t OED (35)
t CAC (18)
t RAC (19)
t LZ (21)
OUT
tCAP (45)
t CAA (20)
t OED (35)
t CAC (18)
tHZ (22)
t DH (33)
t DS (32)
tCAP (45)
t CAA (20)
tHZ (22)
t DH (33)
t DS (32)
t OED (35)
tCAC (18)
t HZ (22)
tDH (33)
t DS (32)
IN
t LZ (21)
OUT
IN
t LZ (21)
OUT
IN
8125H 10
Waveforms of RAS-Only Refresh Cycle
RAS V IH
V IL
CAS V IH
V IL
ADDRESS V IH
V IL
t CRP (13)
t ASR (8)
ROW ADDR
t RAH (9)
NOTE: WE, OE = Donít care
t RC (2)
t RAS (1)
t RP (3)
8125H 11
V53C8125H Rev. 1.7 August 1998
Donít Care
Undefined
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