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PDF V53C316405A50 Data sheet ( Hoja de datos )

Número de pieza V53C316405A50
Descripción 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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No Preview Available ! V53C316405A50 Hoja de datos, Descripción, Manual

MOSEL VITELIC
V53C316405A
3.3 VOLT 4M x 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C316405A
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Extended Data Out Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
50
50 ns
25 ns
20 ns
84 ns
60
60 ns
30 ns
25 ns
104 ns
Features
s 4M x 4-bit organization
s EDO Page Mode for a sustained data rate
of 50 MHz
s RAS access time: 50, 60 ns
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh and Hidden Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
s Single +3.3V ±0.3V Power Supply
s TTL Interface
Description
The V53C316405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access mem-
ory. The V53C316405A offers Page mode opera-
tion with Extended Data Output. The V53C316405A
has asymmetric address, 12-bit row and 10-bit col-
umn.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C316405A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
KT
••
V53C316405A Rev. 1.2 March 1998
Access Time (ns)
50 60
••
1
Power
Std.
Temperature
Mark
Blank

1 page




V53C316405A50 pdf
MOSEL VITELIC
AC Characteristics(5,6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V, tT = 2 ns
# Symbol
Parameter
Common Parameters
1 tRC
2 tRP
3 tRAS
4 tCAS
5 tASR
6 tRAH
7 tASC
8 tCAH
9 tRCD
10 tRAD
11 tRSH
12 tCSH
13 tCRP
14 tT
15 tREF
Read Cycle
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
16 tRAC
17 tCAC
18 tCAA
19 tOEA
20 tRAL
21 tRCS
22 tRCH
23 tRRH
24 tCLZ
25 tOFF
26 tOEZ
27 tDZC
28 tDZO
29 tCDD
30 tODD
Access time from RAS
Access time from CAS
Access time from column address
OE access time
Column address to RAS lead time
Read command setup time
Read command hold time
Read command hold time referenced to RAS
CAS to output in low-Z
Output buffer turn-off delay
Output turn-off delay from OE
Data to CAS low delay
Data to OE low delay
CAS high to data delay
OE high to data delay
V53C316405A
-50
min. max.
-60
min. max. Unit Note
84 – 104 – ns
30 – 40 – ns
50 10k 60 10k ns
8 10k 10 10k ns
0 – 0 – ns
8 – 10 – ns
0 – 0 – ns
8 – 10 – ns
12 37 14 45 ns
10 25 12 30 ns
13 15 – ns
40 50 – ns
5 – 5 – ns
1 50 1 50 ns 7
– 64 – 64 ms
– 50 – 60 ns 8, 9
– 13 – 15 ns 8, 9
– 25 – 30 ns 8,10
– 13 – 15 ns
25 – 30 – ns
0 – 0 – ns
0 – 0 – ns 11
0 – 0 – ns 11
0 – 0 – ns 8
0 13 0 15 ns 12
0 13 0 15 ns 12
0 – 0 – ns 13
0 – 0 – ns 13
10 – 13 – ns 14
10 – 13 – ns 14
V53C316405A Rev. 1.2 March 1998
5

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V53C316405A50 arduino
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
V53C316405A
RAS
CAS
VIH
VIL
VIH
VIL
Address
VIH
VIL
VIH
WE
VIL
VIH
OE
VIL
I/O
(Inputs)
VIH
VIL
I/O
(Outputs)
VOH
VOL
tRAS
tRC
tRP
tRCD
tCSH
tRSH
tCAS
t ASR
t RAD
t ASC
Row
tRAH
t RAL
t CAH
Column
tCWL
tRWL
tWP
tCSH
t ASR
Row
.
tOEH
tDZO
tDZC
tODD
tOEZ
tDH
tDS
tCLZ
tOEA
Valid Data
Hi-Z
Hi-Z
“H” or “L”
WL3
V53C316405A Rev. 1.2 March 1998
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