PDF V437464Q24V Data sheet ( Hoja de datos )

Número de pieza	V437464Q24V
Descripción	3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE
Fabricantes	Mosel Vitelic Corp
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No Preview Available ! MOSEL VITELIC V437464Q24V 3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE PRELIMINARY Features s 168 Pin Unbuffered ECC 67,108,864 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 64M x 4 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL’S Rev 1.2 Module Specification s Single +3.3V (± 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Serial Present Detect (SPD) Description The V437464Q24V memory module is organized 67,108,864 x 72 bits in a 168 pin dual in line memory module (DIMM). The 64M x 72 unbuffered DIMM uses 18 Mosel-Vitelic 64M x 4 ECC SDRAM. The x72 unbuffered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade Configuration V437464Q24VXTG-75PC -75PC, CL=3,2 (133 MHz) 64M x 72 V437464Q24VXTG-75 -75, CL=3 (133 MHz) 64M x 72 V437464Q24VXTG-10PC -10PC, CL=3,2 (100 MHz) 64M x 72 V437464Q24V Rev. 1.0 January 2002 1 1 page MOSEL VITELIC V437464Q24V Serial Presence Detect Information A serial presence detect storage device – E2PROM – is assembled onto the module. Informa- tion about the module configuration, speed, etc. is SPD-Table for modules: written into the E2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) Byte Num- ber Function Described SPD Entry Value 0 Number of SPD bytes 128 1 Total bytes in Serial PD 256 2 Memory Type SDRAM 3 Number of Row Addresses (without BS bits) 13 4 Number of Column Addresses (for x4 SDRAM) 11 5 Number of DIMM Banks 1 6 Module Data Width 72 7 Module Data Width (continued) 0 8 Module Interface Levels LVTTL 9 SDRAM Cycle Time at CL=3 7.5ns/10.0 ns 10 SDRAM Access Time from Clock at CL=3 5.4/6.0 ns 11 Dimm Config (Error Det/Corr.) ECC 12 Refresh Rate/Type Self-Refresh, 15.8µs 13 SDRAM width, Primary x4 14 Error Checking SDRAM Data Width x4 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 16 Burst Length Supported 1, 2, 4, 8 17 Number of SDRAM Banks 4 18 Supported CAS Latencies CL = 2, 3 19 CS Latencies CS Latency = 0 20 WE Latencies WL = 0 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg 22 SDRAM Device Attributes: General Vcc tol ± 10% 23 Minimum Clock Cycle Time at CAS Latency 7.5 ns/10.0 ns =2 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns/6.0 ns 25 Minimum Clock Cycle Time at CL = 1 Not Supported 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 27 Minimum Row Precharge Time 15 ns/20 ns -75PC 80 08 04 0D 0B Hex Value -75 80 08 04 0D 0B -10PC 80 08 04 0D 0B 01 01 01 48 48 48 00 00 00 01 01 01 75 75 A0 54 54 60 02 02 02 80 80 80 04 04 04 04 04 04 01 01 01 0F 0F 0F 04 04 04 06 06 06 01 01 01 01 01 01 00 00 00 0E 0E 0E 75 A0 A0 54 60 60 00 00 00 00 00 00 0F 14 14 V437464Q24V Rev. 1.0 January 2002 5 5 Page MOSEL VITELIC Package Diagram L-DIM-168-30 SDRAM DIMM Module Package 133.37 127.35 V437464Q24V All measurements in mm (4.0 max) 1 10 11 63.68 A 42.18 85 94 95 40 41 B 124 125 84 1.27 ± 0.100 168 6.35 Detail A 2.26 2.0 RADIUS 1.27 + 0.10 6.35 1.27 D 1.0 ± 0.05 3.175 Detail B 2.0 Detail C 0.2 ± 0.15 Tolerances: ± (0.13) unless otherwise specified. V437464Q24V Rev. 1.0 January 2002 11 11 Page

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