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PDF V437432E24V Data sheet ( Hoja de datos )

Número de pieza V437432E24V
Descripción 3.3 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED SDRAM ECC MODULE
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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MOSEL VITELIC
V437432E24V
3.3 VOLT 32M x 72 HIGH PERFORMANCE
REGISTERED SDRAM ECC MODULE
PRELIMINARY
Features
s 168 Pin Registered ECC 33,554,432 x 72 bit
Oganization SDRAM Modules
s Utilizes High Performance 32M x 8 SDRAM in
TSOPII-54 Packages
s Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
s Single +3.3V (± 0.3V) Power Supply
s Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
s Auto Refresh (CBR) and Self Refresh
s All Inputs, Outputs are LVTTL Compatible
s 8192 Refresh Cycles every 64 ms
s Serial Presence Detect (SPD)
Description
The V437432E24V memory module is organized
33,554,432 x 72 bits in a 168 pin dual in line
memory module (DIMM). The 32M x 72 registered
DIMM uses 9 Mosel-Vitelic 32M x 8 ECC SDRAM.
The x72 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
Part Number
Speed
Grade
Configuration
V437432E24VXTG-75PC -75PC, CL=2,3
(133 MHz)
32M x 72
V437432E24VXTG-75
-75, CL=3
(133 MHz)
32M x 72
V437432E24VXTG-10PC -10PC, CL=2,3
(100 MHz)
32M x 72
V437432E24V Rev. 1.0 January 2002
1

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V437432E24V pdf
MOSEL VITELIC
V437432E24V
Serial Presence Detect Information
A serial presence detect storage device –
E2PROM – is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
SPD-Table for modules:
written into the E2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
Byte
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function Described
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8
SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency
=2
Maximum Data Access Time from Clock for
CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL = 1
Minimum Row Precharge Time
SPD Entry Value
128
256
SDRAM
13
10
1
72
0
LVTTL
7.5 ns/10.0 ns
5.4 ns/6.0 ns
ECC
Self-Refresh, 7.8µs
x8
n/a / x8
tccd = 1 CLK
1, 2, 4, 8
4
CL = 2,3
CS Latency = 0
WL = 0
Registered/Buffered.
Vcc tol ± 10%
7.5 ns /10.0 ns
5.4 ns/6.0 ns
Not Supported
Not Supported
15 ns/20 ns
-75PC
80
08
04
0D
0A
Hex Value
-75
80
08
04
0D
0A
-10PC
80
08
04
0D
0A
01 01 01
48 48 48
00 00 00
01 01 01
75 75 A0
54 54 60
02 02 02
82 82 82
08 08 08
08 08 08
01 01 01
0F 0F 0F
04 04 04
06 06 06
01 01 01
01 01 01
1F 1F 1F
0E 0E 0E
75 A0 A0
54 60 60
00 00 00
00 00 00
0F 14 14
V437432E24V Rev. 1.0 January 2002
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V437432E24V arduino
MOSEL VITELIC
Package Dimensions
133.37
127.35
V437432E24V
All measurements in mm
(2.63)
1 10 11
63.68
A
42.18
85 94 95
40 41
B
124 125
84
1.27 ± 0.100
168
6.35
Detail A
2.26
2.0
RADIUS
1.27 + 0.10
6.35
1.27
D
1.0 ± 0.05
3.175
Detail B
2.0
Detail C
0.2 ± 0.15
Tolerances: ± (0.13) unless otherwise specified.
V437432E24V Rev. 1.0 January 2002
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