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PDF V436664Z24V Data sheet ( Hoja de datos )

Número de pieza V436664Z24V
Descripción 512MB 144-PIN UNBUFFERED SDRAM SODIMM/ 64M x 64 3.3 VOLT
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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MOSEL VITELIC
V436664Z24V
512MB 144-PIN UNBUFFERED SDRAM
SODIMM, 64M x 64 3.3 VOLT
PRELIMINARY
Features
JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
Serial Presence Detect with E2PROM
Nonbuffered
Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
Single +3.3V (± 0.3V) Power Supply
All Device Pins are LVTTL Compatible
8192 Refresh Cycles every 64 ms
Self-Refresh Mode
Internal Pipelined Operation; Column Address
can be changed every System Clock
Programmable Burst Lengths: 1, 2, 4, 8
Auto Precharge and Piecharge all Banks by A10
Data Mask Function by DQM
Mode Register Set Programming
Programmable (CAS Latency: 2, 3 Clocks)
SOC and WBGA component packaging
Description
The V436664Z24V memory module is organized
67,108,864 x 64 bits in a 144 pin SODIMM. The
64M x 64 memory module uses 16 Mosel-Vitelic
32M x 8 SDRAM. The x64 modules are ideal for use
in high performance computer systems where
increased memory density and fast access times
are required.
Part Number
Speed
Grade
Configuration
V436664Z24VXXG-75PC -75PC, CL=2,3
(133 MHz)
64M x 64
V436664Z24VXXG-75
-75, CL=3
(133 MHz)
64M x 64
V436664Z24VXXG-10PC -10PC, CL=2
(100 MHz)
64M x 64
32M x 8
32M x 8
32M x 8
32M x 8
1 59 61
Pin 2 on Backside
143
Pin 144 on Backside
V436664Z24V Rev. 1.2 February 2002
1

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V436664Z24V pdf
MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte Num-
ber Function Described
SPD Entry Value
29 Minimum RAS to CAS Delay tRCD
30 Minimum RAS Pulse Width tRAS
31 Module Bank Density (Per Bank)
15 ns/20 ns
42 ns/45 ns
256 Mbyte
64 SDRAM Input Setup Time
1.5 ns/2.0 ns
33 SDRAM Input Hold Time
0.8 ns/ 1.0 ns
34 SDRAM Data Input Setup Time
1.5 ns/2.0 ns
35 SDRAM Data Input Hold Time
0.8 ns/1.0 ns
62-61
Superset Information (May be used in Future)
62 SPD Revision
Revision 2 / 1.2
63 Checksum for Bytes 0 - 62
64 Manufacturer’s JEDEC ID Code
Mosel Vitelic
65-71
Manufacturer’s JEDEC ID Code (cont.)
72 Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436664Z24V
91-92
PCB Identification Code
Current PCB Revision
93 Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94 Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
99-125 Reserved
126 Intel Specification for Frequency
127 Supported Frequency
128+
Unused Storage Location
-75PC
0F
2A
40
15
08
15
08
00
02
FE
40
00
00
64
00
V436664Z24V
Hex Value
-75
14
2D
40
15
08
15
08
00
02
43
40
00
-10PC
14
2D
40
20
10
20
10
00
12
B1
40
00
00 00
64 64
00 00
V436664Z24V Rev. 1.2 February 2002
5

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V436664Z24V arduino
MOSEL VITELIC
Module Label Information
V436664Z24V
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
Module Density
MOSEL VITELIC
V436664Z24VXXX-XX 512MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
Assembly in Taiwan
CAS Latency
2=CL2
3=CL3
PC133 U -XXX 54 2 A
UNBUFFERED DIMM
CL= 3 or 2 (CLK)
tRCD= 3 or 2 (CLK)
tRP= 3 or 2 (CLK)
Gerber file Intel PC100 x8 Based
JEDEC SPD Revision 2
tAC = 5.4 ns
V436664Z24V Rev. 1.2 February 2002
11

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