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PDF V23832-R511-M101 Data sheet ( Hoja de datos )

Número de pieza V23832-R511-M101
Descripción PAROLI 2 Tx AC/ 1.6 Gbit/s
Fabricantes Infineon Technologies 
Logotipo Infineon Technologies Logotipo



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Fiber Optics
Parallel Optical Link Transmitter:
PAROLI® 2 Tx AC, 1.6 Gbit/s
Parallel Optical Link Receiver:
PAROLI® 2 Rx AC, 1.6 Gbit/s
V23832-T2131-M101
V23832-R121-M101
Design Benefits
• Relieve system bandwidth bottle necks
• Simplifies system design
• Enables system upgrades in field
• Low power consumption at increased board density
• Flat package for height critical application
Features
• Infineon’s highly reliable 850 nm VCSEL technology
• Power supply 3.3 V
• Transmitter with multistandard electrical interface
• Receiver with LVDS electrical interface
• 12 electrical data channels
• Asynchronous, AC-coupled optical link
• 12 optical data channels
• Internal power monitoring for constant power budget
• Transmission data rate of up to 1600 Mbit/s per channel,
total link data rate up to 19 Gbit/s
• PIN diode array technology
• Optimized for 62.5 µm multimode graded index fiber
• MT based optical port (MPO connector)
• Plug-in module with ultra low profile
• IEC Class 1M laser eye safety compliant
• GBE mask compliant modules available
• EMI-shielding for front panel access
• Standard link length compliant
• Unused transmitter channels can be switched off
• DC or AC coupling of input data
• Telcordia compliant
File: 3104
PAROLI® is a registered trademark of Infineon Technologies AG
Data Sheet
1
2003-11-19

1 page




V23832-R511-M101 pdf
V23832-T2131-M101
V23832-R121-M101
Pin Configuration
Pin A1 Pin A10
Bottom view
Figure 2 Pin Information Receiver
File: 3332
Numbering Conventions Receiver (bottom view)
JI
HGF E DCB
1 VEE
2 DO04N
3 DO04P
4 DO01N
5 DO01P
6 DO02N
7 DO02P
8 DO03N
9 DO03P
10 VEE
DO05P
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
DO05N DO06P DO06N DO07P DO07N DO08P DO08N
VEE VEE VEE VEE VEE VEE VEE
Reserved Reserved t.b.l.o. t.b.l.o. Reserved Reserved VEE
Reserved Reserved OEN
ENSD Reserved Reserved VEE
VEE VEE SD01 –SD12 VEE VEE VEE
VEE VEE Reserved REFR VEE VEE VEE
VEE
VEE
VCCO
VCCO
VEE
VEE
VEE
VEE
VEE
VCCO
VCCO
VEE
VEE
VEE
VEE VEE VCC VCC VEE VEE VEE
VEE VEE VCC VCC VEE VEE VEE
This edge towards MPO connector
A
VEE
DO09P
DO09N
DO12P
DO12N
DO11P
DO11N
DO10P
DO10N
VEE
Data Sheet 5 2003-11-19

5 Page





V23832-R511-M101 arduino
V23832-T2131-M101
V23832-R121-M101
Description
When Gigabit switching components are found on a PCB (e.g. multiplexer, serializer-
deserializer, clock data recovery, etc.), any opening of the chassis may leak radiation;
this may also occur at chassis slots other than that of the device itself. Thus every
mechanical opening or aperture should be as small as feasible and its length carefully
considered.
On the board itself, every data connection should be an impedance matched line (e.g.
micro strip, strip line or coplanar strip line). Data (D) and Data-not (Dn) should be routed
symmetrically. Vias should be avoided. Where internal termination inside an IC or a
PAROLI module is not present, a line terminating resistor must be provided.
The decision of how best to establish a ground depends on many boundary conditions.
This decision may turn out to be critical for achieving lowest EMI performance. At RF
frequencies the ground plane will always carry some amount of RF noise. Thus the
ground and VCC planes are often major radiators inside an enclosure.
As a general rule, for small systems such as PCI cards placed inside poorly shielded
enclosures, the common ground scheme has often proven to be most effective in
reducing RF emissions. In a common ground scheme, the PCI card becomes more
equipotential with the chassis ground. As a result, the overall radiation will decrease. In
a common ground scheme, it is strongly recommended to provide a proper contact
between signal ground and chassis ground at every location where possible. This
concept is designed to avoid hotspots which are places of highest radiation, caused
when only a few connections between chassis and signal grounds exist. Compensation
currents would concentrate at these connections, causing radiation.
However, as signal ground may be the main cause for parasitic radiation, connecting
chassis ground and signal ground at the wrong place may result in enhanced RF
emissions. For example, connecting chassis ground and signal ground at a front panel/
bezel/chassis by means of a fiber optic module may result in a large amount of radiation
especially where combined with an inadequate number of grounding points between
signal ground and chassis ground. Thus the fiber optic module becomes a single contact
point increasing radiation emissions. Even a capacitive coupling between signal ground
and chassis ground may be harmful if it is too close to an opening or an aperture. For a
number of systems, enforcing a strict separation of signal ground from chassis ground
may be advantageous, providing the housing does not present any slots or other
discontinuities. This separate ground concept seems to be more suitable in huge
systems.
The return path of RF current must also be considered. Thus a split ground plane
between Tx and Rx paths may result in severe EMI problems.
The bezel opening for a transceiver should be sized so that all contact springs of the
transceiver cage make good electrical contact with the face plate.
Please consider that the PCB may behave like a dielectric waveguide. With a dielectric
constant of 4, the wavelength of the harmonics inside the PCB will be half of that in free
space. Thus even the smallest PCBs may have unexpected resonances.
Data Sheet 11 2003-11-19

11 Page







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