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PDF VSC7123QN Data sheet ( Hoja de datos )

Número de pieza VSC7123QN
Descripción 10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Fabricantes ETC 
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No Preview Available ! VSC7123QN Hoja de datos, Descripción, Manual

VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Features
• 802.3z Gigabit Ethernet-Compliant
1.25 Gb/s Transceiver
• ANSI X3T11 Fibre Channel-Compliant
1.0625 Gb/s Transceiver
• 0.98 to 1.36 Gb/s Full-Duplex Operation
• 10-Bit TTL Interface for Transmit and
Receive Data
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
• Automatic Lock-to-Reference
• RX Cable Equalization
• Analog/Digital Signal Detection
• JTAG Access Port for Testability
• Single +3.3V Supply, 650mW Typical
• Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
R(0:9)
10
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
REFCLK
QD
Serial to
Q Parallel D
QD
Comma
Detect
÷10 Clock
÷20 Recovery
2:1
Signal
Detect
RX+
RX-
DQ
x10 Clock
Multiply
Parallel
to Serial
DQ
TX+
TX-
NOT SHOWN: JTAG Boundary Scan
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 1

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VSC7123QN pdf
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Signal Detection
The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre
Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine
if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period,
all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period,
any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.
1) Analog transition detection is performed on the input to verify that the signal swings are of adequate
amplitude. The RX+/- input buffer contains a differential voltage comparator which will go HIGH if the
differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is
between 200mV and 400mV, the output is indeterminate.
2) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
3) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
4) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which
a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data
will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the
monitoring period, SIGDET will go LOW during the next period.
The behavior of SIGDET is affected by EWRAP and ENCDET as shown in Table 1.
Table 1: Signal Detect Behavior
EWRAP
ENCDET
COMDET
Transition
Detect
All Zeros/
All Ones
0
0
Disabled
Enabled
Enabled
0
1
Enabled
Enabled
Enabled
1
0
Disabled
Enabled
Disabled
1
1
Enabled
Enabled
Disabled
Note: COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.
K28.5
Presence
Enabled
Disabled
Disabled
Disabled
Mode
Normal
SIGDET ignores commas
Rollback
Loopback
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in VSC7123/VSC7133 JTAG Access Port Functionality.
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
Page 5

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VSC7123QN arduino
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
DC Characteristics (over recommended operating conditions)
Parameters
Description
Min Typ Max Units
VOH Output HIGH voltage (TTL) 2.4 — —
V
VOL Output LOW voltage (TTL) — — 0.5 V
VIH Input HIGH voltage (TTL) 2.0 5.5 V
VIL Input LOW voltage (TTL)
0 0.8
V
IIH Input HIGH current (TTL) 50 500 µA
IIL Input LOW current (TTL) — — -500 µA
VOUT75(1)
TX output differential peak-
to-peak voltage swing
1200
2200 mVp-p
VOUT50(1)
TX output differential peak-
to-peak voltage swing
1000
2200 mVp-p
VIN(1)
RX Input differential peak-
to-peak input sensitivity
300 2600 mVp-p
VDD
Supply voltage
3.14 3.47
V
PD Power dissipation
650 900 mW
IDD Supply current (all supplies) 190 260 mA
IDDA
Analog supply current
— — 100 mA
NOTE: (1) Refer to Application Note, AN-37, for differential measurement techniques.
Conditions
IOH = 1.0 mA
IOL = +1.0 mA
5V Tolerant Inputs
VIN = 2.4V
VIN = 0.5V
75to VDD 2.0V
(TX+) - (TX-)
50to VDD 2.0V
(TX+) - (TX-)
Internally biased to VDD/2
(RX+) - (RX-)
3.3V±5%
Outputs open,
VDD = VDD max
Outputs open, Case temp =
95oC, VDD = VDD max
VDDA = VDDA max
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
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