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PDF VPX3216B Data sheet ( Hoja de datos )
| Número de pieza | VPX3216B | |
| Descripción | Video Pixel Decoders | |
| Fabricantes | ETC | |
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MICRONAS
INTERMETALL
PRELIMINARY DATA SHEET
VPX 3220 A,
VPX 3216 B,
VPX 3214 C
Video Pixel Decoders
Edition July 1, 1996
6251-368-2PD
MICRONAS
1 page  
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
Video Pixel Decoder Family
Release Notes: Revision bars indicate significant
changes to the previous edition.
1. Introduction
The Video Pixel Decoder (VPX) is a full-feature video ac-
quisition IC for consumer video and multimedia applica-
tions. All of the processing necessary to convert an ana-
log video signal into a digital component stream has
been integrated onto a single 44-pin IC. Its notable fea-
tures include:
– single chip multistandard color decoding NTSC/PAL/
SECAM/S-VHS, NTSC with chroma comb filter.
– two 8-bit video A/D converters with clamping and au-
tomatic gain control (AGC)
– four analog inputs with integrated selector for
3 composite video sources (CVBS), or
2 YC sources (SVHS), or
2 composite video sources and one YC source.
– automatic standard detection
– horizontal and vertical sync detection for all standards
– hue, brightness, contrast, and saturation control
– horizontal resizing between 32 and 1056 pixel/line
– vertical resizing by line dropping
– high quality anti-aliasing filter (VPX 3220 A only)
– ITU-R601 level compatible
– YCbCr (4:4:4, 4:2:2, or 4:1:1) or
γ-corrected RGB 4:4:4 (15, 16, or 24 bits)
compressed Video (DPCM 8 bit)
(VPX 3214 C supports only YCrCb 4:2:2)
– alpha key generation
(only VPX 3220 A, and VPX 3216 B)
– 8-bit or 16-bit synchronous output mode
– asynchronous output mode via FIFO with status flags
– VBI bypass mode for Teletext, Closed Caption, and
Intercast
– 44-pin plastic package (PLCC, TQFP)
– total power consumption under 1 W
– I2C serial control, selectable power-up default state
– on-chip clock generation
– IEEE 1149.1 (JTAG) boundary scan interface
VPX 3220 A, VPX 3216 B, and VPX 3214 C are pin and
software compatible, but differ slightly in the feature set.
1.1. Difference between VPX 3220 A and VPX 3216 B
VPX 3220 A performs low-pass filtering before resam-
pling the data, whereas VPX 3216 B does not. For more
info, see Fig. 1–1 and refer to section 2.3.
1.2. Difference between VPX 3216 B and VPX 3214 C
The VPX 3214 C is based on the VPX 3216 B but without
color space conversion. VPX 3214 C supports only
YCbCr 4:2:2.
1.3. System Architecture
The block diagram in Fig. 1–1 illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The component processing stage resizes
the YCbCr samples, adjusts the contrast and bright-
ness, and interpolates the chroma. The color space
stage contains a dematrix, a γ–1 correction, a DPCM-like
encoder, and an alpha key generator. The format stage
arranges the samples into the selected byte format and
(in the case of asynchronous output) buffers the data for
output.
CVBS/Y
Chroma
Sampling
Sync
Luma
Filter
Y
Chroma
Demod.
Line Store
CbCr
Skew
YCbCr
YCbCr/
RGB
Alpha
Key
Color Decoder
Component
Processing
Color Space
Output
MUX
H/V
Sync
A
B
Clock
Fig. 1–1: Block diagram of the VPX
MICRONAS INTERMETALL
5
5 Page 
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
2.2.9. YCbCr Color Space
The color decoder outputs luminance and two chromi-
nance signals at a sample clock of 20.25 MHz. Active
video samples are flagged by a separate reference sig-
nal. The number of active samples is 1056 for all stan-
dards (525 lines and 625 lines). The representation of
the chroma signals is the ITUR-601 digital studio stan-
dard.
In the following equations, the RGB signals are already
gamma-weighted.
– Y = 0.299*R + 0.587*G + 0.114*B
– (R–Y) = 0.701*R – 0.587*G – 0.114*B
– (B–Y) = –0.299*R – 0.587*G + 0.886*B
In the color decoder, the weighting for both color differ-
ence signals is adjusted individually. The default format
will have the following specification:
– Y = 224*Y + 16 (pure binary),
– Cr = 224*(0.713*(R–Y)) + 128 (offset binary),
– Cb = 224*(0.564*(B–Y)) + 128 (offset binary).
2.3. Component Processing
Recovery of the YCbCr components by the decoder is
followed by horizontal resizing and skew compensation.
Contrast enhancement with noise shaping can also be
applied to the luminance signal. The CbCr samples are
interpolated to create a 4:4:4 format.
Fig. 2–10 illustrates the signal flow through the compo-
nent processing stage. The YCbCr 4:2:2 samples are
separated into a luminance path and a chrominance
path. The Luma Filtering and Chroma Filtering blocks
apply FIR lowpass filters with selectable cutoff frequen-
cies. These filters are available only in VPX 3220 A. The
Resize and Skew blocks alter the effective sampling
rate and compensate for horizontal line skew. The
YCbCr samples are buffered in a FIFO for continuous
read out at a fixed clock rate. In the luminance path, the
contrast and brightness can be varied and noise shaping
applied. In the chrominance path, interpolation is used
to generate a 24-bit/pixel output stream (4:4:4 format).
Yin
Active Video
Reference
VPX 3220 A only
Luma Filter
CbCrin
Chroma Filter
Fig. 2–10: Component processing stage
MICRONAS INTERMETALL
Resize
Skew
Luma
Phase Shift
Sequence
Control
Latch
Chroma
Phase Shift
Resize
Skew
F
I
F
O
16 bit
Contrast &
Brightness
Yout
Cb Cr
Upsampler
Cbout
Crout
11
11 Page | ||
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| PDF Descargar | [ Datasheet VPX3216B.PDF ] | |
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