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PDF VP5511BCGGP1N Data sheet ( Hoja de datos )

Número de pieza VP5511BCGGP1N
Descripción NTSC/PAL Digital Video Encoder
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! VP5511BCGGP1N Hoja de datos, Descripción, Manual

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VP5311B/VP5511B
Supersedes DS4575 1.5 May 1997 version
NTSC/PAL Digital Video Encoder
Advance Information
DS4575 - 2.2 October 1998
The VP5311/VP5511 converts digital Y, Cr, Cb, data
into analog NTSC/PAL composite video and S-video signals.
The outputs are capable of driving doubly terminated 75
ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Y, Cr, Y, Cb
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311/
VP5511 is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
PIN 64
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
PIN
1
FEATURES
2
s
s
s
s
s
s
s
s
s
s
s
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APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Karaoke
s Digital VCRs
18
19
20
21
22
23
24
25
ORDERING INFORMATION
VP5311B/CG/GP1N
VP5511B/CG/GP1N
26
27
28
29
30
31
32
PIN 1 GP64
Figure 1 Pin connections (top view)
FUNCTION
VDD
GND
D0 (VS I/O)
D1 (HS I/O)
D2 (FC0 O/P)
D3 (FC1 O/P)
D4 (FC2 O/P)
D5
D6 (SCSYNC I/P)
D7 (PALID I/P)
GND
VDD
GND
GND
PXCK
VDD
CLAMP
COMPSYNC
GND
VDD
TDO
TDI
TMS
TCK
GND
SA1
SA2
SCL
VDD
SDA
GND
VDD
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FUNCTION
VDD
RESET
REFSQ
GND
VDD
GND
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
VDD
AGND
VREF
DACGAIN
COMP
AVDD
LUMAOUT
AGND
COMPOUT
AGND
CHROMAOUT
AVDD
N/C
N/C
AVDD
AVDD
N/C
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PIN DESCRIPTIONS
Pin Name
PD0-7
D0-7
PXCK
CLAMP
COMPSYNC
TDO
TDI
TMS
TCK
SA1
SA2
SCL
SDA
RESET
REFSQ
VREF
DAC GAIN
COMP
LUMAOUT
COMPOUT
CHROMAOUT
NOT USED
VDD
AVDD
GND
AGND
Pin No.
39 - 46
3 - 10
15
17
18
21
22
23
24
26
27
28
30
34
35
50
51
52
54
56
58
60, 61, 64
1, 12, 16,
20, 29,
32, 33,
37, 48
53, 59
62, 63
2, 11, 13,
14, 19,
25, 31,
36, 38, 47
49, 55, 57
Description
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
46. These pins are internally pulled low.
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 3.
These pins are internally pulled low.
27MHz Pixel Clock input. The VP5311 internally divides PXCK by two to provide the pixel
clock.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
JTAG Data scan output port.
JTAG Data scan input port.
JTAG Scan select input.
JTAG Scan clock input.
Slave address select.
Slave address select.
Standard I2C bus serial clock input.
Standard I2C bus serial data input/output.
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311.
Reference square wave input used only during Genlock mode.
Voltage reference output. This output is nominally 1·055V and should be decoupled with a
100nF capacitor to GND.
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GND sets the
a reference current
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flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 52 and pin
53.
True luminance, composite and chrominance video signal outputs. These are high
impedance current source outputs. A DC path to GND must exist from each of these pins.
Positive supply input. All VDD pins must be connected.
Analog positive supply input. All AVDD pins must be connected.
Negative supply input. All GND pins must be connected.
Negative supply input. All AGND pins must be connected.
All other pins are N/C and should not be connected.
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VP5311B/VP5511B
PXCK Input (27MHz)
HS
Nck=2
Nck=0
t SU; PD
t HD; PD
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Pixel Data Input (PD[7,0])
Figure 4 REC 656 interface with HS output timing
REFSQ
SC_SYNC
REFSQ
2:1 mux
0 fSC
Divide by 4
Synchronous Q
Counter
RESET
1 Input to
Genlocking
Block
FSC4_SEL
(register bit)
1/ f SC_SYNC
t PWH; SC_SYNC
tSU; SC_SYNC
SC_SYNC
t HD; SC_SYNC
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Q
Figure 5 REFSQ and SC_SYNC input timing
Pixel Data Input (PD[7,0\)
Sample Number
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
Y719 $FF $00 $00 $XY
ANCILLARY DATA...
EAV SEQUENCE
t SU; PD
t PWL; PXCK
PXCK Input (27MHz)
t PWH; PXCK
t HD; PD
t DUR; PAL_ID
t SU; PAL_ID
t HD; PAL_ID
Input (PAL_ID)
PAL_ID Stable
Figure 6 PAL_ID input timing
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