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PDF VP5313ACGGP1N Data sheet ( Hoja de datos )

Número de pieza VP5313ACGGP1N
Descripción NTSC/PAL Digital Video Encoder
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! VP5313ACGGP1N Hoja de datos, Descripción, Manual

VP5313/VP5513
NTSC/PAL Digital Video Encoder
Supersedes DS4509 1.9 September 1997 edition
DS4509 - 2.2 October 1998
The VP5313/VP5513 converts digital Y Cr Cb data into
analog PAL or NTSC composite video, and also provides
33 23
simultaneous RGB outputs. These additional converters can
optionally provide separate luma and chroma outputs plus a
further composite video channel. All outputs are capable of
driving doubly terminated 75loads with standard video
34
22
levels.
All D/A converters are to 9 bit accuracy, and are provided with
27MHz oversampled data. The latter simplifies the
requirement for external analog anti-aliasing filters, and
reduces the sinx/x distortion inherent in D/A converters.
Separate digital scaling is applied to the chroma data path in
order to make the most efficient use of the 9 bit dynamic range.
The device accepts data inputs complying with CCIR
44
12
recommendation 656. In this format 4:2:2 video is multiplexed
onto an 8 bit bus using a 27MHz clock. Active video markers
are embedded into the data stream and extracted by the
VP5313/VP5513. Optionally the user can supply separate
1 11 GP44
horizontal and vertical syncs, and colour can be genlocked to
an external subcarrier if necessary.
In an alternative operating mode the VP5313/VP5513 can
be configured as the source of sync for the rest of the system.
Fig.1 Pin connections (top view)
PIN FUNCTION
1 VDD
PIN FUNCTION
23 SCL
In this master mode the horizontal and vertical sync pins
2
PD5
24 SDA
become outputs, and any control codes in the CCIR656 bit
3
stream are ignored.
4www.DataSheet4U.com
The VP5313/VP5513 supports the insertion of teletext
data through a serial interface. An internal filter shapes the
data edges.
5
6
7
PD6
PD7
CLAMP
COMPSYNC
PALID
25 DACCOMP
26 RED/C
27 GREEN/Y
28 AVDD
29 AGND
FEATURES
s Converts Y, Cr, Cb data to analog RGB and composite
or S-video and composite video
s Supports CCIR recommendations 601 and 656
s All digital video encoding
s Selectable master/slave mode for sync signals
s Switchable chrominance bandwidth
s CCIR 624 PAL SMPTE or 170M NTSC compatible
outputs
s GENLOCK mode
s I2C bus serial microprocessor interface
s Only VP5313 supports Macrovision anti-taping
Rev. 7.01
s Line 21 Closed Caption encoding
s Teletext insertion, fully line programmable
8 SCSYNC
9 REFSQ
10 GND
11 VDD
12 FC2
13 FC1
14 FC0
15 HSYNC
16 VSYNC
17 TTXREQ
18 SA
19 TTXDATA
20 VDD
21 GND
22 RESET
30 AVDD
31 BLUE/CVBS2
32 CVBS1
33 VREF
34 RREF
35 AGND
36 AGND
37 AVDD
38 PD0
39 PD1
40 PD2
41 PD3
42 PD4
43 GND
44 PXCK
APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Digital VCRs
s Karaoke
ORDERING INFORMATION
VP5313A/CG/GP1N
VP5513A/CG/GP1N

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VP5313ACGGP1N pdf
VP5313/VP5513
SDA
SCL
SA
RESETB
TTXDATA
TTXREQ
I2C INTERFACE
TELETEXT
CONTROL
TELETEXT
SHAPING
FILTER
SET-UP
REGISTERS
ANTI-TAPING
CONTROL
YCrCb
YCrCb to
RGB
YCrCb
8 INPUT YUV
DEMUX
PD7-0
INTERPOLATING
FILTERS
Y
UV
PXCK
HSYNC
VSYNC
FC0-2
3
COMPSYNC
CLAMP
VIDEO TIMING GENERATOR
REFSQ
SCSYNC
PALID
DIGITAL
PHASE COMP
+
SYNC
INSERT
MODULATOR
+
COLOUR SUBCARRIER
GENERATOR
Figure 2 Functional block diagram
CLOSED
CAPTION
MUX
9 BIT
DAC
9 BIT
DAC
G/Y
B/CVBS2
9 BIT
DAC
R/C
9 BIT
DAC
CVBS1
DAC
REF
RREF
VREF
DACCOMP
V
W
H
Peak Glitch Area = H x W/2
The glitch energy is calculated by measuring the area under the voltage
time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)
T(ps)
Figure 3 Glitch Energy (see Peak Glitch Energy in table on page 2)
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VP5313ACGGP1N arduino
The horizontal line duration for PAL equates to 1728
CLK27M cycles and within each line there are 444 data bit
periods. The duration of 37 data bits (the smallest number
possible for an integer number of CLK27M cycles) therefore
equates to 144 CLK27M cycles.
To ensure that the average bit rate is 6.9375 MHz, 33 in
every 37 data bits will have a duration of 4 CLK27M cycles and
4 in every 37 data bits will have a duration of 3 CLK27M cycles.
Of the first 37 data bits in each line, bits 10, 19, 28 and 37 will
VP5313/VP5513
have a duration of 3 CLK27M cycles. The sequence will be
repeated for all subsequent 37 bit groups.
Master Reset
The VP5313/VP5513 must be initialised with RESET. This
is an asynchronous, active low signal and must be active for
a minimum of 200ns in order to reset the VP5313/VP5513.
The device resets to line 64, start of horizontal sync (i.e. line
blanking active). There is no on-chip power on reset circuitry.
CVBS/Y
TTX_DATA
textbit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TTXDD
434
434
TTX_REQ
NCO Adjustment
Figure 4 Teletext timing diagram
Standard
Lines/ Field
field freq. HZ
NTSC
525 59.94
PAL-B, G, H, I (d) 625 50
PAL-N (Argentina) 625 50
Number of
pixels/line
at 27MHz
1716
1728
1728
Horizontal
freq. kHz.
fH
15.734266
15.625000
15.625000
Subcarrier
freq. kHz.
fSC
3.57954545
fSC/fH
(455/2)
SC_ADJ
register
hex
xx
4.43361875 (1135/4+1/625) 9C
3.58205625 (917/4+1/625) 57
FREQ2-0
registers hex
87 C1 F1
A8 26 2B
87 DA 51
(d) = default
xx = don’t care.
Table.2 Line, field and subcarrier standards and register settings
The calculation of the FREQ register value is according to the following formula:-
FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz
NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I.
PXCK Input (27MHz)
HS
Nck=2
Nck=0
t SU; PD
t HD; PD
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Pixel Data Input (PD[7,0])
Figure 5 REC 656 interface with HS output timing
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