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PDF VP215 Data sheet ( Hoja de datos )

Número de pieza VP215
Descripción Dual 90MHz 6-Bit Analog to Digital Converter
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! VP215 Hoja de datos, Descripción, Manual

VP215
Dual 90MHz 6-Bit Analog to Digital Converter
Preliminary Information
DS4068 - 1.4 May 1996
The VP215 is a dual 90MHz 6-bit Analog to Digital
Converter designed for use in consumer satellite receivers
and decoders, video systems, multimedia and
communications applications.
Operating from a single +5V supply, the VP215 includes
an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC
and digital I/O that can be interfaced to either +5V or +3V.
The VP215 also has the necessary bias voltages for the
reference resistor chain in the 'flash' architecture of the ADC.
FEATURES
s 90MHz Conversion Rate
s TTL Clock/Data Interface
s 0.5 Volt Analog Input Range
s Internal ADC Reference
s Digital I/O’s compatible with +5V or +3V logic
s Single 5 Volt Supply
s Dual ADC System for good channel matching
APPLICATIONS
s Satellite Decoders
s Multimedia
s Communications
www.DataSheet4U.com
ORDERING INFORMATION
VP215A CG MP1S (Commercial - 28 pin plastic SO)
CLKIN
VCCD
DGND
VRT
COMPA
VINA
AGND
VCCA
VRM
COMPB
VINB
VRB
N.C.
N.C.
1
2
3
4
5
6
7
8 VP215
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DA5
DA4
DA3
DA2
DA1
DA0
OGND
VCCO
DB5
DB4
DB3
DB2
DB1
DB0
MP28
Fig.1 Pin connections - top view (wide body)
--------V-CC-D--------------VC-C-A --------------VC-CO--------
28
21
5
COMPA
6
VINA
9
VRM
ADC
DRIVER
+
6-BIT
ADC
VRB VRM VRT
6 LATCHES
DATA
OUTPUTS
23 DA0
24 DA1
25 DA2
26 DA3
27 DA4
28 DA5
VRB 12
VREF
OP AMPS
CLOCK
DRIVER
1
CLKIN
VRT 4
VINB 11
COMPB
10
+
ADC
DRIVER
VRB VRM VRT
6-BIT
ADC
LATCHES
6
DATA
OUTPUTS
15 DB0
16 DB1
17 DB2
18 DB3
19 DB4
20 DB5
----------3----------------7---------------2-2-------
DGND
AGND
OGND
Fig.2 System block diagram

1 page




VP215 pdf
VP215
Device Description
The VP215 is a dual 90MHz 6-bit ADC system, (see
Fig.2). Included on chip is a high bandwidth ADC driver
amplifier, a 6-bit analog to digital converter, latches and TTL
compatible data outputs. The VP215 also has the necessary
bias voltages for the reference resistor chain in the ‘flash’
architecture of the ADC.
Analog Input
The analog inputs, (VIN A,B) are A.C. coupled into the
non-inverting input of the ADC driver amplifiers, which
provide the necessary bandwidth, gain, offset and low
impedance required to drive the ADC. The amplifier has
been designed so that an input of 0 volts will produce an
output level equal to the voltage present at the middle of the
ADC resistor chain, VRM (3.00V typ.). This is achieved by an
internal feedback loop within each amplifier which compares
the amplifier output with VRM, (see Fig.3). This voltage will
produce a transition binary code of 011111 to 100000 at the
output of the ADC.
Reference Voltage
An on chip band gap voltage reference circuit combined
with two op-amps provides all the necessary bias voltages
for the ADC reference resistor chain, bottom (VRB), middle
(VRM) and top(VRT). VRB, VRM and VRT have been
brought out to pins 12, 9 and 4 respectively and should be
decoupled with 100nF capacitors close to the package pins.
ADC Circuit
The VP215 employs a ‘flash’ architecture consisting of a
reference resistor chain, an array of 64 comparators,
encoding logic and a 6-bit latch. The 63 reference levels
generated by the resistor chain are compared with the
analog output signal from the ADC driver amplifier using the
comparator array. This produces a thermometer code which
the encoding logic converts into a 6-bit word.
VRM
INPUT
SIGNAL
CC
ADC DRIVER
AMP
DC SHIFT
TO ADC
COMP_(Q,I)
CCOMP
Fig.3 DC offset internal feedback loop
Digital Interface
The TTL data output pins, (DA0-DA5) and (DB0-DB5),
have been optimized to interface with devices in close
proximity to the VP215 and are designed to provide
satisfactory logic levels at speeds up to 90MHz into a fanout
of one and a total load capacitance of 10pF. All data outputs
should have approximately equivalent loading to ensure
proper setup and hold times. For capacitive loads in excess
of 10pF, output buffers are recommended.
Clock Interface
The clock signal to the ADC synchronizes the sampling,
conversion and output stages of the device as shown in the
timing diagram (see Fig.4). The output of the ADC driver amp
is sampled when the comparator array is latched on the rising
edge of the input clock. Data is then presented to the TTL data
outputs and latched on the falling edge of the input clock.
VIN(A,B)
V ref.
Comparator
C
Latch
L
τ1
Data Out
Clock to ADC
N-1
N
N+1
VIN(A,B)
CLKIN
Data Outputs
Tpw 1
Tpw 0
N-1 N N+1
Tsu THold
Fig.4 System timing diagram
TTL
Threshold
5

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