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Número de pieza | VP2110 | |
Descripción | P-Channel Enhancement-Mode Vertical DMOS FETs | |
Fabricantes | Supertex Inc | |
Logotipo | ||
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No Preview Available ! VP2110
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
► Free from secondary breakdown
► Low power drive requirement
► Ease of paralleling
► Low CISS and fast switching speeds
► Excellent thermal stability
► Integral source-to-drain diode
► High input impedance and high gain
Applications
General Description
The Supertex VP2110 is an enhancement-mode (normally-
off) transistor that utilizes a vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors, and the
high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
► Motor controls
► Converters
► Amplifiers
► Switches
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
Package Options
TO-236AB (SOT-23)
Die*
BVDSS/BVDGS
(V)
VP2110
VP2110K1-G
-G indicates package is RoHS compliant (‘Green’)
* MIL visual screening available
VP2110ND
-100
Pin Configuration
DRAIN
RDS(ON)
(max)
(Ω)
12
ID(ON)
(min)
(mA)
-500
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Soldering temperature*
300OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
SOURCE
GATE
TO-236AB (SOT-23) (K1)
Product Marking
P1AW
W = Code for Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-236AB (SOT-23) (K1)
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page 3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
VP2110
Top View
Side View
View B
View B
View A - A
Symbol
A A1 A2 b
MIN 0.89 0.01 0.88 0.30
Dimension
(mm)
NOM
-
- 0.95 -
MAX 1.12 0.10 1.02 0.50
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO236ABK1, Version C041309.
D
2.80
2.90
3.04
E
2.10
-
2.64
E1
1.20
1.30
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
θ
0O
-
8O
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009
All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-VP2110
A041309
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
5
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet VP2110.PDF ] |
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