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PDF VIPER20B Data sheet ( Hoja de datos )

Número de pieza VIPER20B
Descripción SMPS PRIMARY I.C.
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! VIPER20B Hoja de datos, Descripción, Manual

VIPer20B
® VIPer20BSP
TYPE
VIPer20B/ SP
VDSS
400V
In
1.3 A
RDS(on)
8.7
FEATURE
s ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
s CURRENT MODE CONTROL
s SOFT START AND SHUT DOWN CONTROL
s AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM (1W TOTAL POWER
CONSUMPTION)
s INTERNALLY TRIMMED ZENER
REFERENCE
s UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s INTEGRATED START-UP SUPPLY
s AVALANCHE RUGGED
s OVERTEMPERATURE PROTECTION
s LOW STAND-BY CURRENT
s ADJUSTABLE CURRENT LIMITATION
BLOCK DIAGRAM
SMPS PRIMARY I.C.
PRELIMINARY DATA
10
PENTAWATT HV
1
Power SO-10
DESCRIPTION
VIPer20Bcombines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (400V 1.3A).
Typical applications cover off line power supplies
with a secondary max power capability of 30W. It
is compatible from both primary or secondary
regulation loop despite using around 50% less
components when compared with a discrete
solution. Burst mode operation is an additional
feature of this device, offering the possibility to
operate in stand-by mode without extra
components.
OSC
DRAIN
VDD
ON/OFF
OSCILLATOR
UVLO
LOGIC
SECURITY
LATCH
R/S FF Q
S
PWM
LATCH
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V
ERROR
AMPLIFIER
_
+
_
13 V +
4.5 V
2 µs
delay
300 ns
Blanking
September 1999
COMP
0.5V
++ _
6 V/A
_
CURRENT
AMPLIFIER
SOURCE
1/17

1 page




VIPER20B pdf
VIPer20B / VIPer20BSP
ELECTRICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER SECTION
S ymb ol
VDDreg
VDDreg
GBW
P a ra m et er
VDD Regulation Point
Total Variation
Unity Gain Bandwidth
A VOL
Gm
V COMPL O
V C OM PHI
ICOMPLO
I CO MP HI
Open Loop Voltage
Gain
DC Transconductance
Output Low Level
Output High Level
Output Low Current
Capability
Output High Current
Capability
Test Conditions
ICOMP = 0 mA (see fig.1)
TJ = 0 to 100 oC
From Input = VDD t o Out put = VCOMP
CO MP pin is open (see fig. 8)
CO MP pin is open (see fig. 8)
VCOMP = 2.5 V (see fig. 1)
ICOMP = -400 µA
VDD = 14 V
ICOMP = 400 µA
VDD = 12 V
VCOMP = 2.5 V
VDD = 14 V
VCOMP = 2.5 V
VDD = 12 V
Min.
12.6
TBD
TBD
Typ .
13
2
150
50
1.5
0.2
4.5
-600
600
Max.
13.4
Unit
V
%
KHz
dB
TBD
mA/V
V
V
µA
µA
PWM COMPARATOR SECTION
S ymb ol
HID
VCOMPo f f
IDpeak
td
tb
P a ra m et er
Test Conditions
VCOMP /IDpea k
VCOMP offset
VCOMP = 1 t o 3 V
IDpeak = 10 mA
Peak Current Limitation VDD = 12 V COMP pin open
Current Sense Delay
to turn-off
ID = 0.4 A
Blanking Time
Min.
TBD
1.3
Typ .
2.3
0.5
250
Max.
TBD
TBD
Unit
V/A
V
A
ns
300 ns
SHUTDOWN AND OVERTEMPERATURE SECTION
S ymb ol
V COMP th
tDI Ss u
Ttsd
Thyst
P a ra m et er
Restart threshold
Disable Set Up Time
Thermal Shutdown
Temperature
Thermal Shutdown
Hy s t e r es is
Test Conditions
(see fig. 4)
(see fig. 4)
(see fig. 6)
(see fig. 6)
Min.
140
Typ .
0.5
1.7
160
Max.
5
Unit
V
µs
oC
34 oC
5/17

5 Page





VIPER20B arduino
VIPer20B / VIPer20BSP
OPERATION DESCRIPTION :
CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer20B uses two control loops
- an inner current control loop and an outer loop
for voltage control. When the Power MOSFET
output transistor is on, the inductor current
(primary side of the transformer) is monitored with
a SenseFET technique and converted into a
voltage VS proportional to this current. When VS
reaches VCOMP (the amplified output voltage
error) the power switch is switched off. Thus, the
outer voltage control loop defines the level at
which the inner loop regulates peak current
through the power switch and the primary winding
of the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
following the dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power PSTBY
given by :
PSTBY
=
1
2
LP
IS2 TBY
FSW
Where:
LP is the primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as :
IST BY
=
(tb
+ td)
LP
VIN
tb + td is the sum of the blanking time and of the
propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that PSTBY
may be affected by the efficiency of the converter
at low load, and must include the power drawn on
the primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP < VCOMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer20B to meet the new German ”Blue Angel”
Norm with 1W total power consumption for the
system when working in stand-by. The output
voltage remains regulated around the normal
level, with a low frequency ripple corresponding
to the burst mode. The amplitude of this ripple is
low, because of the output capacitors and of the
low output current drawn in such conditions.The
normal operation resumes automatically when the
power get back to higher levels than PSTBY.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage current source
provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are
placed into a standby mode with reduced
11/17

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