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PDF X76F100P-3.0 Data sheet ( Hoja de datos )

Número de pieza X76F100P-3.0
Descripción 1K 128 x 8 Bit
Fabricantes Xicor 
Logotipo Xicor Logotipo



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1K
X76F100
128 x 8 Bit
Secure SerialFlash
FEATURES
• 64-bit password security
• One array (112-bytes) two passwords (16-bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (rst input)
• 8-byte sector Write Mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—3.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead PDIP, SOIC, MSOP, and smart car module
DESCRIPTION
The X76F100 is a Password Access Security Supervi-
sor, containing one 896-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F100 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F100 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F100 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
CS
SCL
SDA
Interface
Logic
RST
Chip Enable
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
Reset
Response Register
8K Byte
SerialFlash Array
Array 0
(Password Protected)
32 Byte
SerialFlash Array
Array 1
(Password Protected)
Retry Counter
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 1 of 16

1 page




X76F100P-3.0 pdf
X76F100
Data ACK Polling Sequence
Write Sequence
Completed
Enter ACK Polling
Issue START
Issue New
Command Code
Password ACK Polling Sequence
Password Load
Completed
Enter ACK Polling
Issue START
Issue Password
ACK Command
ACK
returned?
YES
PROCEED
NO
ACK
returned?
YES
PROCEED
NO
After the password sequence, there is always a nonvol-
atile write cycle. This is done to discourage random
guesses of the password if the device is being tam-
pered with. In order to continue the transaction, the
X76F100 requires the master to perform a password
ACK polling sequence with the specific command code
of 55h. As with regular Acknowledge polling the user
can either time out for 10ms, and then issue the ACK
polling once, or continuously loop as described in the
flow.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the password ACK polling sequence is
over.
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the
password is incorrect until the 10ms write cycle time
has elapsed.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the
read command. Once the password has been acknowl-
edged data may be read from the sector. An acknowl-
edge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector,
but may stop at any time. Random accesses to the
array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array and data can
continue to be read out. After the last bit has been
read, a stop condition is generated without sending a
preceding acknowledge.
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 5 of 16

5 Page





X76F100P-3.0 arduino
X76F100
RST Timing Diagram—Response to a Synchronous Reset
tSR
CS
RST
CLK
tNOL
I/O
tRST
1st
CLK
Pulse
tRDV
tNOL
tSU:RST
tHIGH_RST
2nd
CLK
Pulse
tCDV
Data Bit (1)
tLOW_RST
3rd
CLK
Pulse
Data Bit (2)
CS
RST
CLK
I/O
Data Bit (N)
Data Bit (N+1)
tDHZ
(N+2)
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
80
RMAX
60
40
20
RMIN
20 40 60 80 100
Bus Capacitance in pF
RMIN = -V--I---OC----CL----MM-----IA-N---X--- = 1.8K
RMAX = C-----B-t---R-U-----S--
tR = maximum allowable SDA rise time
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 11 of 16

11 Page







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