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PDF X5643P-4.5A Data sheet ( Hoja de datos )

Número de pieza X5643P-4.5A
Descripción CPU Supervisor with 64Kbit SPI EEPROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X5643P-4.5A Hoja de datos, Descripción, Manual

Replaces X25643/X25645
X5643/X5645
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—8-lead PDIP, 14-lead SOIC
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
VCC
Watchdog Transition
Detector
Protect Logic
Data
Register
Command
Decode &
Control
Logic
Status
Register
16Kbits
16Kbits
VCC Threshold
Reset logic
32Kbits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power On and
Low Voltage
Reset
Generation
RESET/RESET
X5643 = RESET
X5645 = RESET
REV 1.1.1 3/5/01
www.xicor.com
Characteristics subject to change without notice. 1 of 19

1 page




X5643P-4.5A pdf
X5643/X5645
Figure 4. Sample VTRIP Reset Circuit
VTRIP
Adj.
Program
4.7K
+
NC
18
27
3 X5643/45 6
45
NC 4.7K
RESET
NC
VP
10K 10K
Reset VTRIP
Test VTRIP
Set VTRIP
SPI SERIAL MEMORY
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the status regis-
ter. The status register may be read at any time, even dur-
ing a write cycle.The status register is formatted as follows:
7 65 43210
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
WREN
SFLB
0000 0110
0000 0000
WRDI/RFLB
0000 0100
RSDR
WRSR
0000 0101
0000 0001
READ
WRITE
0000 0011
0000 0010
Operation
Set the write enable latch (enable write operations)
Set flag bit
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
REV 1.1.1 3/5/01
www.xicor.com
Characteristics subject to change without notice. 5 of 19

5 Page





X5643P-4.5A arduino
X5643/X5645
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
COUT(2)
CIN(2)
Test
Output Capacitance (SO, RESET/RESET)
Input Capacitance (SCK, SI, CS, WP)
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Max.
8
6
Unit
pF
pF
Conditions
VOUT = 0V
VIN = 0V
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V 5V
2.06K
4.6K
Output
3.03K
RESET/RESET
100pF
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
tSU
tH
tRI(3)
tFI(3)
tCS
tWC(4)
Clock frequency
Cycle time
CS lead time
CS lag time
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
Parameter
2.7–5.5V
Min.
Max.
02
500
250
250
200
250
50
50
100
100
500
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
REV 1.1.1 3/5/01
www.xicor.com
Characteristics subject to change without notice. 11 of 19

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