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PDF X5083S8 Data sheet ( Hoja de datos )

Número de pieza X5083S8
Descripción CPU Supervisor with 8Kbit SPI EEPROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X5083S8 Hoja de datos, Descripción, Manual

X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lockmemory
—Block lock first or last page, any 1/4 or lower 1/2
of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
—16 byte page write mode
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Set Top Boxes
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
• Battery Powered Equipment
Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
BLOCK DIAGRAM
VCC
CS/WDI
SI
SO
SCK
WP
VTRIP
+
-
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
8Kbits
RESET (X5083)
X5083
Standard VTRIP Level
4.63V (+/-2.5%)
Suffix
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 21 for
more details
For Custom Settings, call Xicor.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 1 of 21

1 page




X5083S8 pdf
X5083
Figure 4. VTRIP Programming Sequence
New VCC Applied =
Old VCC Applied + Error
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
NO RESET pin
goes active?
YES
Error –Emax
Emax = Maximum Desired Error
Measured VTRIP -
Desired VTRIP
Error Emax
–Emax < Error < Emax
DONE
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus
activity within the user selectable time out period or the
supply voltage falls below a preset minimum VTRIP.
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 5 of 21

5 Page





X5083S8 arduino
X5083
Figure 11. End of Nonvolatile Write (no Polling)
tWC
CS
SCK
SI
Non-volatile
Write
Operation
0 1 2 3 4 56 7
NEXT
INSTRUCTION
Wait tWC after a write for new operation,
if not using polling procedure
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 11 of 21

11 Page







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