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PDF X5045M8I-2.7 Data sheet ( Hoja de datos )

Número de pieza X5045M8I-2.7
Descripción CPU Supervisor with 4K SPI EEPROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X5045M8I-2.7 Hoja de datos, Descripción, Manual

4K
X5043/X5045
512 x 8 Bit
CPU Supervisor with 4K SPI EEPROM
FEATURES
• Selectable time out watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<10µA max standby current, watchdog off
—<2mA max active current during read
• 2.7V to 5.5V and 4.5V to 5.5V power supply
versions
• 4Kbits of EEPROM–1M write cycle endurance
• Save critical data with Block Lockmemory
—Protect 1/4, 1/2, all or none of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• 3.3MHz clock rate
• Minimize programming time
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead MSOP, 8-lead SOIC, 8-pin PDIP
—14-lead TSSOP
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscil-
lator to stabilize before the processor executes code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
1Kbits
1Kbits
2Kbits
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET/RESET
X5043 = RESET
X5045 = RESET
Power on and
VCC + Low Voltage
Reset
VTRIP
-
Generation
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 1 of 20

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X5045M8I-2.7 pdf
X5043/X5045
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied
=
Old VCC Applied
- Error
Execute
Set VTRIP
Sequence
New VCC Applied
=
Old VCC Applied
- Error
Apply 5V to VCC
Decrement VCC
(VCC = VCC–10mV)
Execute
Reset VTRIP
Sequence
NO RESET pin
goes active?
YES
Error -Emax
Measured VTRIP
-Desired VTRIP
Error Emax
-Emax < Error < Emax
DONE
Emax = Maximum Desired Error
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x8 bits. The device fea-
tures a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that
controls the operation of the device. The instruction
code is written to the device via the SI input. There are
two write operations that requires only the instruction
byte. There are two read operations that use the
instruction byte to initiate the output of data. The
remainder of the operations require an instruction byte,
an 8-bit address, then data bytes. All instruction,
address and data bits are clocked by the SCK input. All
instructions (Table 1), addresses and data are trans-
ferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static,
allowing the user to stop the clock and then start it
again to resume operations where left off. CS must be
LOW during the entire operation.
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RSDR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 A8011
0000 A8010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 5 of 20

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X5045M8I-2.7 arduino
X5043/X5045
Equivalent A.C. Load Circuit at 5V VCC
5V 5V
1.64K
4.6K
Output
1.64K
RESET/RESET
30pF
30pF
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
tSU
tH
tRI(3)
tFI(3)
tCS
tWC(4)
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
Parameter
2.7V–5.5V
Min.
Max.
0 3.3
300
150
150
130
130
30
30
2
2
100
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ms
Data Output Timing
Symbol
fSCK
tDIS
tV
tHO
tRO(3)
tFO(3)
Parameter
Clock Frequency
Output Disable Time
Output Valid from Clock Low
Output Hold Time
Output Rise Time
Output Fall Time
2.7–5.5V
Min.
Max.
0 3.3
150
120
0
50
50
Unit
MHz
ns
ns
ns
ns
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 11 of 20

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