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PDF X40626S14 Data sheet ( Hoja de datos )

Número de pieza X40626S14
Descripción Dual Voltage CPU Supervisor with 64K Serial EEPROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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Preliminary Information
64K
X40626
8K x 8 Bit
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET is asserted until VCC returns to proper
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
RESET
Power on and
Low Voltage
VCC
+ Reset
VTRIP
-
Generation
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 1 of 23

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X40626S14 pdf
X40626
Figure 4. VTRIP Programming Sequence
VTRIPX Programming
No Desired
VTRIPX
Present Value
YES
Set VX = Desired VTRIPX
New VX applied =
Old VX applied + | Error |
NO
Execute
Set Higher VTRIPX Sequence
Execute
Set Higher VX Sequence
Apply VCC and Voltage
> Desired VTRIPX to VX
Decrease VX
Vx = VCC, V2MON
Let: MDE = Maximum Desired Error
MDE+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
New VX applied =
Old VX applied - | Error |
Execute Reset VTRIPX
Sequence
Error < MDE
Output Switches?
YES
Actual VTRIPX -
Desired VTRIPX
Error > MDE+
| Error | < | MDE |
DONE
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 5 of 23

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X40626S14 arduino
X40626
Figure 11. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
Nonvolatile Cycle
complete. Continue
command sequence?
NO
NO
Issue STOP
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address in the
address counter is 00H.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Figure 12. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t Slave
a Address
r
t
1 0 1 0 0 S1 S0 1
A
C
K
Data
S
t
o
p
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 11 of 23

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