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PDF X4003S8-4.5A Data sheet ( Hoja de datos )

Número de pieza X4003S8-4.5A
Descripción CPU Supervisor
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X4003S8-4.5A Hoja de datos, Descripción, Manual

X4003/X4005
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 1 of 18

1 page




X4003S8-4.5A pdf
X4003/X4005
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC–50mV)
New VCC Applied =
Old VCC applied + Error
RESET pin
goes active?
YES
Error Emax
Measured VTRIP -
Desired VTRIP
-Emax < Error < Emax
DONE
NO
Error –Emax
Emax = Maximum Allowable VTRIP Error
Control Register
The control register provides the user a mechanism for
changing the watchdog timer settings. watchdog timer
bits are nonvolatile and do not change when power is
removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a control
register write operation. Only one data byte is allowed
for each register write operation. Prior to writing to the
control register, the WEL and RWEL bits must be set
using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register"
below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 5 of 18

5 Page





X4003S8-4.5A arduino
X4003/X4005
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol
COUT(4)
CIN(4)
Parameter
Output capacitance (SDA, RESET/RESET)
Input capacitance (SCL, WP)
Note: (4) This parameter is periodically sampled and not 100% tested.
Max.
8
6
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
EQUIVALENT A.C. LOAD CIRCUIT
5V 5V
SDA
1533
For VOL = 0.4V
and IOL = 3 mA
100pF
RESET
RESET
4.6K
100pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1VCC to 0.9VCC
10ns
0.5VCC
Standard output load
A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
tSU:WP
tHD:WP
Cb
Parameter
SCL clock frequency
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus free before start of new transmission
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
SDA and SCL rise time
SDA and SCL fall time
WP setup time
WP hold time
Capacitive load for each bus line
100kHz
Min. Max.
0 100
n/a n/a
0.1 0.9
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
1000
300
0.4
0
400
400kHz
Min.
Max.
0 400
50
0.1 0.9
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(6) 300
20 +.1Cb(6) 300
0.6
0
400
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 11 of 18

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