DataSheet.es    


PDF X40014V8-C Data sheet ( Hoja de datos )

Número de pieza X40014V8-C
Descripción Dual Voltage Monitor with Integrated CPU Supervisor
Fabricantes Xicor 
Logotipo Xicor Logotipo



Hay una vista previa y un enlace de descarga de X40014V8-C (archivo pdf) en la parte inferior de esta página.


Total 25 Páginas

No Preview Available ! X40014V8-C Hoja de datos, Descripción, Manual

New Features
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
Preliminary Datasheet
X40010/X40011/X40014/X40015
Dual Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms,
1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second voltage monitor circuit
tracks the unregulated supply to provide a power fail
warning or monitors different power supply voltage.
Three common low voltage combinations are avail-
able, however, Xicor’s unique circuits allows the
BLOCK DIAGRAM
SDA
SCL
VCC
(V1MON)
V2MON
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
Watchdog Timer
and
Reset Logic
User Programmable
VTRIP1
User Programmable
VTRIP2
+
-
V2MON
+ VCC
Power on,
Low Voltage
Reset
Generation
-
*X40010/11 = V2MON*
X40014/15 = VCC
WDO
RESET
X40010/14
RESET
X40011/15
V2FAIL
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 1 of 25

1 page




X40014V8-C pdf
X40010/X40011/X40014/X40015 – Preliminary
Setting a Lower VTRIPx Voltage (x=1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1 and 0Bh for VTRIP2, followed by 00h for the
Data Byte in order to reset VTRIPx. The STOP bit fol-
lowing a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of VTRIPx becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/
11/14/15 will not acknowledge any data bytes written
after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus proto-
col, but a stop is not required to end this operation.
765 4
PUP1 WD1 WD0 BP
3 2 10
0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample VTRIP Reset Circuit
VTRIP1
Adj.
V2FAIL
RESET
VTRIP2
Adj.
4.7K
18
3 SOIC 7
2 X4001x 6
45
VP
Adjust
Run
µC
SCL
SDA
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 5 of 25

5 Page





X40014V8-C arduino
X40010/X40011/X40014/X40015 – Preliminary
Figure 10. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
Returned?
YES
NO
High Voltage Cycle
Complete. Continue
Command Sequence?
YES
Continue Normal
Read or Write
Command Sequence
Issue STOP
NO
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condi-
tion and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 13. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000H and the device continues to out-
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
REV 1.3.4 7/12/02
www.xicor.com
Characteristics subject to change without notice. 11 of 25

11 Page







PáginasTotal 25 Páginas
PDF Descargar[ Datasheet X40014V8-C.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
X40014V8-ADual Voltage Monitor with Integrated CPU SupervisorXicor
Xicor
X40014V8-BDual Voltage Monitor with Integrated CPU SupervisorXicor
Xicor
X40014V8-CDual Voltage Monitor with Integrated CPU SupervisorXicor
Xicor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar