DataSheet.es    


PDF X28C010RMB-12 Data sheet ( Hoja de datos )

Número de pieza X28C010RMB-12
Descripción 5 Volt/ Byte Alterable E2PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



Hay una vista previa y un enlace de descarga de X28C010RMB-12 (archivo pdf) en la parte inferior de esta página.


Total 25 Páginas

No Preview Available ! X28C010RMB-12 Hoja de datos, Descripción, Manual

X28C010
1M
X28C010
5 Volt, Byte Alterable E2PROM
128K x 8 Bit
FEATURES
Access Time: 120ns
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 50mA
—Standby: 500µA
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
DESCRIPTION
The Xicor X28C010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C010 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28C010 supports Software Data
Protection option.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
PIN CONFIGURATIONS
CERDIP
FLAT PACK
SOIC (R)
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
X28C010
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3858 FHD F02.1
PGA
I/O0 I/O2 I/O3 I/O5 I/O6
15 17 19 21 22
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
A2 A3
12 11
A10 OE
25 26
A4
10
A6
8
A5
9
A7
7
X28C010
(BOTTOM VIEW)
A11 A9
27 28
A8 A13
29 30
A12 A15 NC VCC NC NC A14
6 5 2 36 34 32 31
A16 NC NC WE NC
4 3 1 35 33
3858 FHD F20
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3858-3.1 4/3/97 T1/C0/D0 SH
1
PLCC
LCC
30
A7
A6
5 4 3 2 32 31 29
6 1 28
A14
A13
A5 7
27 A8
A4
A3
8 26
9
X28C010
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20
21
I/O7
EXTENDED LCC
30
4 3 2 32 31
1
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
A4
A3
8 26
9
X28C010
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0 13
21 I/O7
14 15 16 17 18 19 20
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP
3858 FHD F03.1
X28C010
40 OE
39 A10
38 CE
37 I/O7
36 I/O6
35 I/O5
34 I/O4
33 I/O3
32 NC
31 NC
30 VSS
29 NC
28 NC
27 I/O2
26 I/O1
25 I/O0
24 A0
23 A1
22 A2
21 A3
3858 ILL F21
Characteristics subject to change without notice

1 page




X28C010RMB-12 pdf
X28C010
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
HIGH Z
*
X28C010
READY
3858 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
COMPARE
OK?
YES
X28C010
READY
NO
3858 FHD F15
5

5 Page





X28C010RMB-12 arduino
X28C010
POWER-UP TIMING
Symbol
tPUR(2)
tPUW(2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
CI/O(2)
CIN(2)
Input/Output Capacitance
Input Capacitance
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Endurance
Data Retention
Min.
10,000
100,000
100
Max.
100
5
Max.
10
10
Units
pF
pF
Max.
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
Input and Output
Timing Levels
10ns
1.5V
3858 PGM T05.1
MODE SELECTION
CE OE WE
L LH
LHL
HXX
XLX
XXH
Mode
Read
Write
Standby and
Write Inhibit
Write Inhibit
Write Inhibit
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
Units
µs
ms
3858 PGM T05
Test Conditions
VI/O = 0V
VIN = 0V
3858 PGM T06
Units
Cycles Per Byte
Cycles Per Page
Years
3858 PGM T07.1
I/O
DOUT
DIN
High Z
Power
Active
Active
Standby
——
——
3858 PGM T08
5V
1.92K
OUTPUT
1.37K
100pF
3858 FHD F04.3
Note: (2) This parameter is periodically sampled and not 100%
tested.
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11

11 Page







PáginasTotal 25 Páginas
PDF Descargar[ Datasheet X28C010RMB-12.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
X28C010RMB-125 Volt/ Byte Alterable E2PROMXicor
Xicor
X28C010RMB-155 Volt/ Byte Alterable E2PROMXicor
Xicor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar