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PDF X25F128SE Data sheet ( Hoja de datos )

Número de pieza X25F128SE
Descripción SerialFlash Memory With Block Lock Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X25F128SE Hoja de datos, Descripción, Manual

APPLICATION NOTE
A V A I LABLE
X25F128AN61 • AN75 • AN77 • AN79 • AN82
X25F128
16K x 8 Bits
SerialFlash™ Memory With Block Lock™ Protection
FEATURES
• 1MHz Clock Rate
• SPI Serial Interface
• 16K X 8 Bits
— 32 Byte Small Sector Program Mode
• Low Power CMOS
— <1µA Standby Current
— <5mA Active Current
• 1.8V – 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
• Block Lock Protection
— Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Program Protection
— Power-Up/Power-Down protection circuitry
— Program Enable Latch
— Program Protect Pin
• Self-Timed Program Cycle
— 5ms Program Cycle Time (Maximum)
• High Reliability
— Endurance: 100,000 cycles per byte
— Data Retention: 100 Years
— ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 16-Lead 150 mil SOIC Package
DESCRIPTION
The X25F128 is a 131,072-bit CMOS SerialFlash
memory, internally organized 16K X 8. It features a
“Univolt” Program and Read voltage, Serial Peripheral
Interface (SPI), and software protocol allowing operation
on a simple three-wire bus. The bus signals are a clock
input (SCK), plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a chip
select (CS) input, allowing any number of devices to
share the same bus.
The X25F128 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25F128 will ignore transitions on
its inputs, thus allowing the host to service higher priority
interrupts. The PP input can be used as a hardwire input
to the X25F128 disabling all program attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering 0, 1/4, 1/2, or all of the
memory.
The X25F128 utilizes Xicor’s proprietary flash cell, pro-
viding a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
CS
HOLD
COMMAND
DECODE
AND CONTROL
LOGIC
X
DECODE
LOGIC
STATUS
REGISTER
DATA REGISTER
SECTOR DECODE LOGIC
32 8
MEMORY
ARRAY
PP
PROGRAMMING
CONTROL LOGIC
SerialFlash™ and Block Lock™ Protection are trademarks of Xicor, Inc.
© Xicor, Inc. 1995, 1996 Patents Pending
6829-1.9 4/7/97 T3/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
6829 ILL F01.1
Characteristics subject to change without notice

1 page




X25F128SE pdf
X25F128
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The program enable latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent programming:
• The program enable latch is reset upon power-up.
• A program enable instruction must be issued to set
the program enable latch.
CS must come HIGH at the proper clock count in
order to start a program cycle.
Figure 1. Read SerialFlash Memory Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
SI
15 14 13
3210
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
6829 ILL F03
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
6829 ILL F04
5

5 Page





X25F128SE arduino
X25F128
Hold Timing
CS
SCK
SO
SI
HOLD
tHD
tHZ
tCD tCD
tHD
tLZ
6829 ILL F12
11

11 Page







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