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Número de pieza | X25C02MI | |
Descripción | SPI Serial E2PROM | |
Fabricantes | Xicor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de X25C02MI (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! APPLICATION NOTES
AVA I L A B L E
X25C02AN9 • AN18 • AN31 • AN37 • AN40
2K
X25C02
SPI Serial E2PROM
256 x 8 Bit
FEATURES
• 1MHz Clock Rate
• 256 X 8 Bits
—4 Byte Page Mode
• Low Power CMOS
—150µA Standby Current
—2mA Active Current
• 5V Power Supply
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• Available Packages
—8-Lead MSOP
—8-Lead PDlP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E2PROM, inter-
nally organized as 256 x 8. The X25C02 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25C02 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
The X25C02 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3843-1.6 6/10/96 T5/C1/D1 NS
X 64
DECODE
LOGIC
256 BYTE ARRAY
(64 X 32)
48
Y DECODE
DATA REGISTER
3843 FHD F01
Characteristics subject to change without notice
1
1 page X25C02
Operational Notes
The X25C02 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read Operation Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
The “write enable” latch is reset when WP is brought LOW.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
SI
BYTE ADDRESS
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
3843 FHD F04.1
Figure 2. Set Write Enable Latch Sequence
CS
SCK
01234567
SI
HIGH IMPEDANCE
SO
3843 FHD F05.1
5
5 Page X25C02
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.118 ± 0.002
(3.00 ± 0.05)
0.0256 (0.65) TYP
0.118 ± 0.002
(3.00 ± 0.05)
R 0.014 (0.36)
0.030 (0.76)
0.036 (0.91)
0.032 (0.81)
0.0216 (0.55)
7° TYP
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.007 (0.18)
0.005 (0.13)
0.150 (3.81)
REF.
0.193 (4.90)
REF.
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3926 ILL F49
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet X25C02MI.PDF ] |
Número de pieza | Descripción | Fabricantes |
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