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PDF X25650S8-2.5 Data sheet ( Hoja de datos )

Número de pieza X25650S8-2.5
Descripción 5MHz SPI Serial E 2 PROM with Block Lock TM Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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64K
X25650
8K x 8 Bit
5MHz SPI Serial E2PROM with Block LockTM Protection
FEATURES
5MHz Clock Rate
Low Power CMOS
<1µA Standby Current
<5mA Active Current
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
32 Byte Page Mode
Block Lock™ Protection
Protect 1/4, 1/2 or all of E2PROM Array
Programmable Hardware Write Protection
In-Circuit Programmable ROM Mode
Built-in Inadvertent Write Protection
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
Self-Timed Write Cycle
5ms Write Cycle Time (Typical)
High Reliability
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
Packages
8-Lead SOIC
20-Lead TSSOP
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25650 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25650 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25650 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25650 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25650 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25650 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
64
64
128
8K BYTE
ARRAY
64 X 256
64 X 256
128 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7037–1.5 6/19/97 T1/C0/D0 SH
1
32 8
Y DECODE
DATA REGISTER
7037 FRM F01
Characteristics subject to change without notice

1 page




X25650S8-2.5 pdf
X25650
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
VCC or tied to VCC through a resistor.
Figure 1. Read E2PROM Array Operation Sequence
Operational Notes
The X25650 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent in-
advertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
15 14 13
3 210
HIGH IMPEDANCE
SO
Figure 2. Read Status Register Operation Sequence
76
MSB
DATA OUT
5432 10
7037 FRM F03
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
7037 FRM F04
5

5 Page





X25650S8-2.5 arduino
X25650
Hold Timing
CS
SCK
SO
SI
HOLD
tHD
tHZ
tCD tCD
tHD
tLZ
7037 FRM F12
11

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