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PDF X25329V14I-2.7 Data sheet ( Hoja de datos )

Número de pieza X25329V14I-2.7
Descripción V CC Supervisory Circuit w/Serial E 2 PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X25329V14I-2.7 Hoja de datos, Descripción, Manual

64K
X25648/49,
8K x 8 Bit
32K
X25328/29,
4K x 8 Bit
16K
X25168/69
2K x 8 Bit
VCC Supervisory Circuit w/Serial E2PROM
FEATURES
DESCRIPTION
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<1µA Max Standby Current
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
These devices combines two popular functions, Supply
Voltage Supervision and Serial E2PROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
The user’s system is protected from low voltage condi-
tions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
32 8
SERIAL
E2PROM
ARRAY
VCC
LOW
VOLTAGE
SENSE
PROGRAMMING,
WP BLOCK LOCK &
ICP ROM CONTROL
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7032 -1.1 6/17/97 T1/C0/D0 SH
1
HIGH
VOLTAGE
CONTROL
7036 FRM 01
Characteristics subject to change without notice

1 page




X25329V14I-2.7 pdf
X25648/49, X25328/29, X25168/69
While the write is in progress following a Status Register
or E2PROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
RESET/RESET Operation
The RESET (X25XX3) output is designed to go LOW
whenever VCC has dropped below the minimum trip point,
Vtrip.
The RESET (X25XX5) output is designed to go HIGH
whenever VCC has dropped below the minimum trip point,
Vtrip.
The RESET/RESET output is an open drain output and
requires a pull up resistor.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
Figure 1. Read E2PROM Array Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
SI
HIGH IMPEDANCE
SO
16 BIT ADDRESS
15 14 13
3210
DATA OUT
7 654321 0
MSB
7036 FRM 03
5

5 Page





X25329V14I-2.7 arduino
X25648/49, X25328/29, X25168/69
Serial Output Timing
CS
SCK
SO
t CYC
tV
MSB OUT
MSB–1 OUT
tHO
tWH
t WL
t LAG
LSB OUT
tDIS
SI
ADDR
LSB IN
Serial Input Timing
CS
SCK
SI
tLEAD
tSU t H
MSB IN
HIGH IMPEDANCE
SO
tCS
tLAG
tRI t FI
LSB IN
11

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