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PDF X25320VM-2.7 Data sheet ( Hoja de datos )

Número de pieza X25320VM-2.7
Descripción SPI Serial E2PROM With Block LockTM Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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APPLICATION NOTE
AVA I L A B L E
X25320
AN61
32K
X25320
4K x 8 Bit
SPI Serial E2PROM With Block LockTM Protection
FEATURES
• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 4K X 8 Bits
— 32 Byte Page Mode
• Low Power CMOS
— <1µA Standby Current
— <5mA Active Current During Write
• 2.7V To 5.5V Power Supply
• Block Lock Protection
— Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
— Power-Up/Power-Down protection circuitry
— Write Enable Latch
— Write Protect Pin
• Self-Timed Write Cycle
— 5ms Write Cycle Time (Typical)
• High Reliability
— Endurance: 100,000 cycles
— Data Retention: 100 Years
— ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
• 14-Lead TSSOP Package
DESCRIPTION
The X25320 is a CMOS 32768-bit serial E2PROM,
internally organized as 4K x 8. The X25320 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25320 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25320 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25320 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25320 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
X DECODE
LOGIC
32
32
64
4K BYTE
ARRAY
32 X 256
32 X 256
64 X 256
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3063-3.9 6/11/96 T4/C1/D0 NS
1
32 8
Y DECODE
DATA REGISTER
3063 ILL F01
Characteristics subject to change without notice

1 page




X25320VM-2.7 pdf
X25320
Operational Notes
The X25320 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
SI
15 14 13
3210
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
3063 ILL F03
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
3063 ILL F04
5

5 Page





X25320VM-2.7 arduino
X25320
Hold Timing
CS
SCK
SO
SI
HOLD
tHD
tHZ
tCD tCD
tHD
tLZ
3063 ILL F12.1
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11

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