DataSheet.es    


PDF X25166S14I-2.7 Data sheet ( Hoja de datos )

Número de pieza X25166S14I-2.7
Descripción Programmable Watchdog Timer w/Serial E 2 PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



Hay una vista previa y un enlace de descarga de X25166S14I-2.7 (archivo pdf) en la parte inferior de esta página.


Total 15 Páginas

No Preview Available ! X25166S14I-2.7 Hoja de datos, Descripción, Manual

64K
X25644/46
8K x 8 Bit
32K
X25324/26
4K x 8 Bit
16K
X25164/66
2K x 8 Bit
Programmable Watchdog Timer w/Serial E2PROM
FEATURES
• Programmable Watchdog Timer with Reset
Assertion
—Reset Signal Valid to Vcc=1V
—Power Up Reset Control
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564x)
—14-Lead TSSOP (X2532x, X2516x)
—8-Lead SOIC (X2532x, X2516x)
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
DESCRIPTION
These devices combine two popular functions, Watchdog
Timer, and Serial E2PROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET/RESET signal
after a selectable time-out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
32 8
SERIAL
E2PROM
ARRAY
WATCHDOG
TIMER
WRITE,
WP BLOCK LOCK &
ICP ROM CONTROL
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7050 -1.0 6/20/97 T0/C0/D0 SH
1
HIGH
VOLTAGE
CONTROL
7029 FRM 01
Characteristics subject to change without notice

1 page




X25166S14I-2.7 pdf
X25644/46
X25324/26
X25164/66
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0” .
While the write is in progress following a Status Register
or E2PROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
RESET/RESET Operation
The RESET (X25xx4) output is designed to go LOW
whenever the Watchdog timer has reached its program-
mable time-out limit.
The RESET (X25xx6) output is designed to go HIGH
whenever the watchdog timer has reached its program-
mable time-out limit.
The RESET/RESET output is an open drain output and
requires a pull up resistor.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for tPURST
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
Figure 1. Read E2PROM Array Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
SI
HIGH IMPEDANCE
SO
16 BIT ADDRESS
15 14 13
3210
DATA OUT
7 654321 0
MSB
7029 FRM 03
5

5 Page





X25166S14I-2.7 arduino
X25644/46
X25324/26
X25164/66
CS vs. RESET/RESET Timing
CS
RESET
RESET
t CST
t WDO
tRST
tWDO
t RST
Power Up and Down Timing Diagram
VCC
VRST
tPURST
7029 FRM 11
RESET
RESET
RESET/RESET Output Timing
Symbol
tWDO
tCST
tRST
tPURST
VRST
Parameter
Watchdog Timeout Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
CS Pulse Width to Reset the Watchdog
Reset Timeout
Power Up Reset Timeout
Reset Valid Voltage
Min.
100
450
1
400
100
100
1.0
Typ.
200
600
1.4
200
7029 FRM 12
Max.
300
800
2
300
350
Units
ms
ms
sec
ns
ms
ms
V
7029 FRM T15
11

11 Page







PáginasTotal 15 Páginas
PDF Descargar[ Datasheet X25166S14I-2.7.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
X25166S14I-2.7Programmable Watchdog Timer w/Serial E 2 PROMXicor
Xicor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar