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PDF X25128PM Data sheet ( Hoja de datos )

Número de pieza X25128PM
Descripción SPI Serial E 2 PROM with Block Lock TM Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X25128PM Hoja de datos, Descripción, Manual

APPLICATION NOTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E2PROM with Block LockTM Protection
16K x 8 Bit
FEATURES
2MHz Clock Rate
SPI Modes (0,0 & 1,1)
16K X 8 Bits
—32 Byte Page Mode
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
14-Lead SOIC Package
16-Lead SOIC Package
8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25128 is a CMOS 131,072-bit serial E2PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
128
256
16K BYTE
ARRAY
16 X 256
16 X 256
32 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
32 8
Y DECODE
DATA REGISTER
3091 FM F01
©Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
Characteristics subject to change without notice
1

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X25128PM pdf
X25128
be low when HOLD is first pulled low and SCK must
also be low when HOLD is released.
The HOLD input may be tied high either directly to VCC
or tied to VCC through a resistor.
Operational Notes
The X25128 powers-up in the following state:
• The device is in the low power standby state.
• A high to low transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come high at the proper clock count in
order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
SI
15 14 13
3210
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
3091 FM F03
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
543210
3091 FM F04
5

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X25128PM arduino
X25128
Hold Timing
CS
SCK
SO
SI
HOLD
tHD
tHZ
tCD t CD
t HD
t LZ
3091 FM F12.1
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
May change
from LOW
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11

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