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PDF X25021PI-2.7 Data sheet ( Hoja de datos )

Número de pieza X25021PI-2.7
Descripción SPI Serial E2PROM with Block LockTM Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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X25021
2K
X25021
256 x 8 Bit
SPI Serial E2PROM with Block LockTM Protection
FEATURES
1MHz Clock Rate
SPI Modes (0,1 & 1,0)
256 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—10µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
8-Lead SOIC Package
DESCRIPTION
The X25021 is a CMOS 2048-bit serial E2PROM, inter-
nally organized as 256 x 8. The X25021 features a Serial
Peripheral Interface (SPI) and software protocol allow-
ing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25021 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25021 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25021 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25021 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1995, 1996 Patents Pending
6615-1.5 6/10/96 T3/C1/D0 NS
1
X DECODE
LOGIC
16
16
32
256 BYTE
ARRAY
16 X 32
16 X 32
32 X 32
48
Y DECODE
DATA REGISTER
6615 FHD F01
Characteristics subject to change without notice

1 page




X25021PI-2.7 pdf
X25021
Operational Notes
The X25021 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
BYTE ADDRESS
SI 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
DATA OUT
76543210
MSB
6615 FHD F14
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
6615 ILL F13
5

5 Page





X25021PI-2.7 arduino
X25021
Hold Timing
CS
SCK
SO
SI
HOLD
tHD
tHZ
tCD tCD
tHD
tLZ
6615 FHD F11
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11

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