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PDF X24C08S14-3 Data sheet ( Hoja de datos )

Número de pieza X24C08S14-3
Descripción Serial E2PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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XPr2e4liCm0in8ary Information
8K
X24C08
1024 x 8 Bit
Serial E2PROM
TYPICAL FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50 µA
Internally Organized 1024 x 8
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8 Pin Mini-DlP, 8 Pin SOIC and 14 Pin
SOIC Packages
DESCRIPTION
The X24C08 is a CMOS 8,192 bit serial E2PROM,
internally organized 1024 x 8. The X24C08 features a
serial interface and software protocol allowing operation
on a simple two wire bus.
The X24C08 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24C08 utilizes Xicor’s proprietary Direct Write™
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(7) TEST
(5) SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(6) SCL
(3) A2
(2) A1
(1) A0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
PIN
XDEC
E2PROM
64 X 128
YDEC
8
CK DATA REGISTER DOUT
3842 FHD F01
© Xicor, 1991 Patents Pending
3842-1
1 Characteristics subject to change without notice

1 page




X24C08S14-3 pdf
X24C08
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C08 this is fixed as
1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
HIGH
ORDER
WORD
ADDRESS
1 0 1 0 A2 A1 A0 R/W
DEVICE
ADDRESS
3842 FHD F09
The next bit addresses a particular device. A system
could have up to two X24C08 devices on the bus (see
Figure 10). The two addresses are defined by the state
of the A2 input.
The next two bits of the slave address field are an
extension of the array’s address and are concatenated
with the eight bits of address in the word address field,
providing direct access to the whole 1024 x 8 array.
Figure 5. Byte Write
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24C08 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A2
input.) Upon a correct compare the X24C08 outputs an
acknowledge on the SDA line. Depending on the state
of the R/W bit, the X24C08 will execute a read or write
operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C08 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
1024 words in the array. Upon receipt of the word
address the X24C08 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24C08 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24C08 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
S
T
BUS ACTIVITY: A
MASTER
R
T
SLAVE
ADDRESS
WORD
ADDRESS
SDA LINE
S
BUS ACTIVITY:
X24C08
AA
CC
KK
DATA
S
T
O
P
P
A
C
K
3842 FHD F10
5

5 Page





X24C08S14-3 arduino
X24C08
WRITE CYCLE LIMITS
Symbol
tWR(6)
Parameter
Write Cycle Time
Min.
Typ.(5)
5
Max.
10
Units
ms
3842 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24C08
bus interface circuits are disabled, SDA is allowed to
remain high, and the device does not respond to its slave
address.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
STOP
CONDITION
tWR
START
CONDITION
X24C08
ADDRESS
3842 FHD F05
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
120
100
RMIN
=
VCC MAX
IOL MIN
=1.8K
80
RMAX
=tRMAX
CBUS
60 MAX.
RESISTANCE
40
20 MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
3842 FHD F17
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
11

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