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PDF X24C02M-3 Data sheet ( Hoja de datos )

Número de pieza X24C02M-3
Descripción Serial E2PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X24C02M-3 Hoja de datos, Descripción, Manual

XPr2e4liCm0in2ary Information
2K
X24C02
Serial E2PROM
256 x 8 Bit
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 µA
Internally Organized 256 x 8
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
New Hardwire—Write Control Function
DESCRIPTION
The X24C02 is CMOS a 2048 bit serial E2PROM,
internally organized 256 x 8. The X24C02 features a
serial interface and software protocol allowing operation
on a simple two wire bus. Three address inputs allow up
to eight devices to share a common two wire bus.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years. Available in DIP,
MSOP and SOIC packages.
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(7) WC
(5) SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(6) SCL
(3) A2
(2) A1
(1) A0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
PIN
XDEC
E2PROM
64 X 32
YDEC
8
CK DATA REGISTER DOUT
3838 FHD F01
© Xicor, 1991 Patents Pending
3838-1.2 7/30/96 T0/C3/D1 SH
1 Characteristics subject to change without notice

1 page




X24C02M-3 pdf
X24C02
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24C02 this is fixed as 1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
1 0 1 0 A2 A1 A0 R/W
DEVICE
ADDRESS
3838 FHD F09
The next three significant bits address a particular
device. A system could have up to eight X24C02 devices
on the bus (see Figure 10). The eight addresses are
defined by the state of the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operations is selected.
Figure 5. Byte Write
Following the start condition, the X24C02 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A0,
A1 and A2 inputs). Upon a correct compare the X24C02
outputs an acknowledge on the SDA line. Depending on
the state of the R/W bit, the X24C02 will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C02 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24C02 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24C02 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24C02 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
S
T
BUS ACTIVITY: A
MASTER
R
T
SLAVE
ADDRESS
WORD
ADDRESS
SDA LINE
S
BUS ACTIVITY:
X24C02
AA
CC
KK
DATA
S
T
O
P
P
A
C
K
3838 FHD F010
Figure 6. Page Write
S
T
BUS ACTIVITY: A
MASTER
R
T
SDA LINE
S
BUS ACTIVITY:
X24C02
SLAVE
ADDRESS
WORD
ADDRESS (n)
AA
CC
KK
DATA n
DATA n+1
AA
CC
KK
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
DATA n+3
S
T
O
P
P
A
C
K
3838 FHD F011
5

5 Page





X24C02M-3 arduino
X24C02
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
tWR(6)
Write Cycle Time
5 10 ms
3838 PGM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the X24C02 bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
STOP
CONDITION
tWR
START
CONDITION
X24C02
ADDRESS
3838 FHD F05
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
RMIN
=
VCC MAX
IOL MIN
=1.8K
80
RMAX
=
tR
CBUS
60 MAX.
RESISTANCE
40
20 MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
3838 FHD F17
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
11

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