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PDF X24645S8-2.7 Data sheet ( Hoja de datos )

Número de pieza X24645S8-2.7
Descripción Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection
Fabricantes Xicor 
Logotipo Xicor Logotipo



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Preliminary Information
64K
X24645
8192 x 8 Bit
Advanced 2-Wire Serial E2PROM with Block LockTM Protection
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
Internally Organized 8192 x 8
New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the E2PROM
array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead SOIC (JEDEC)
—20-Lead TSSOP
DESCRIPTION
The X24645 is a CMOS 65,536-bit serial E2PROM,
internally organized 8192 x 8. The X24645 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
Two device select inputs (S1, S2) allow up to four
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, 1FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24645 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24645 with WP tied to VCC,
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected, as long
as WP remains HIGH.
FUNCTIONAL DIAGRAM
WP
VCC
VSS
SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &
CONTROL
WRITE PROTECT
REGISTER AND
LOGIC
SCL
S2
S1
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
PIN
XDEC
E2PROM
256 X 256
YDEC
8
CK DATA REGISTER DOUT
2783 ILL F01
©Xicor, 1995, 1996 Patents Pending
2783-3.5 5/13/96 T1/C0/D0 NS
Characteristics subject to change without notice
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X24645S8-2.7 pdf
X24645
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to four X24645’s on the bus. The four
addresses are defined by the state of the S1 and S2
inputs. S2 of the slave address must be the inverse of
the S2 input pin.
Figure 4. Slave Address
DEVICE
SELECT
HIGH ORDER
ADDRESS
BITS
S2 S1 A12 A11 A10 A9 A8 R/W
2783 ILL F07.1
The next five bits of the slave address are an exten-
sion of the array’s address and are concatenated with
the eight bits of address in the byte address field,
providing direct access to the whole 8192 x 8 array.
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24645 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24645 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24645 requires a second ad-
dress field. This address field is the byte address, com-
prised of eight bits, providing access to any one of 8192
words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24645 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
BUS ACTIVITY:
X24645
BYTE
ADDRESS
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
2783 ILL F08.1
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X24645S8-2.7 arduino
X24645
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X24645.......................................–65°C to +135°C
Storage Temperature ........................–65°C to +150°C
Voltage on any Pin with
Respect to VSS.................................... –1V to +7V
D.C. Output Current ..............................................5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0°C
+70°C
Industrial
–40°C
+85°C
Military
–55°C
+125°C
2783 FRM T04
D.C. OPERATING CHARACTERISTICS
Supply Voltage
X24645
X24645-2.7
Limits
4.5V to 5.5V
2.7V to 5.5V
2783 FRM T05
Limits
Symbol
ICC1
ICC2
Parameter
VCC Supply Current (Read)
VCC Supply Current (Write)
ISB1(1)
VCC Standby Current
Min.
ISB2(1)
VCC Standby Current
ILI
ILO
VlL(2)
VIH(2)
VOL
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
–1
VCC x 0.7
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Max.
1
3
50
1
10
10
VCC x 0.3
VCC + 0.5
0.4
Units
Test Conditions
mA SCL = VCC X 0.1/VCC X 0.9 Levels
mA
@ 100KHz, SDA = Open, All Other
Inputs = VSS or VCC – 0.3V
µA SCL = SDA = VCC, All Other
Inputs = VSS or VCC – 0.3V,
VCC = 5V ± 10%
µA SCL = SDA = VCC, All Other
Inputs = VSS or VCC – 0.3V,
VCC = 2.7V
µA VIN = VSS to VCC
µA VOUT = VSS to VCC
V
V
V IOL = 3mA, VCC = 4.5V
2783 FRM T06.2
Symbol
CI/O(3)
CIN(3)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (S1, S2, SCL)
Notes: (1) Must perform a stop command prior to measurement.
(2) VIL min. and VIH max. are for reference only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
Max.
8
6
Units
pF
pF
Test Conditions
VI/O = 0V
VIN = 0V
2783 FRM T07.1
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