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PDF X24641S8 Data sheet ( Hoja de datos )

Número de pieza X24641S8
Descripción 400 KHz 2-Wire Serial E 2 PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X24641S8 Hoja de datos, Descripción, Manual

64K
X24641
8K x 8 Bit
400 KHz 2-Wire Serial E2PROM
FEATURES
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Operation
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Internally Organized 8K x 8
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Hardware Write Protect
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 1,000,000 Cycles
—Data Retention: 100 Years
8-Lead SOIC
DESCRIPTION
The X24641 is a CMOS Serial E2PROM Memory,
internally organized 8K x 8. The device features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24641. When the WP
pin is HIGH, the upper quadrant of the Serial E2PROM
array is protected against any nonvolatile write
attempts.
Xicor Serial E2PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
FUNCTIONAL DIAGRAM
SERIAL E2PROM DATA
AND ADDRESS (SDA)
SCL
COMMAND
DECODE
AND
CONTROL
LOGIC
S2
DEVICE
S1 SELECT
LOGIC
S0
PAGE
DECODE
LOGIC
WRITE
PROTECT
LOGIC
DATA REGISTER
Y DECODE LOGIC
E2PROM
ARRAY
8K x 8
WRITE VOLTAGE
WP CONTROL
7026 FM 01
©Xicor, 1995, 1996 Patents Pending
7026 3/27/97 T0/C0/D0 SH
Characteristics subject to change without notice
1

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X24641S8 pdf
X24641
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S0, S1, and S2. This allows up to 8
devices to share a single bus. These bits are
compared to the S0, S1, and S2 device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a Read Operation is selected. When it is zero
then a Write Operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E2PROM array is 256
pages by 32 bytes per page. The page address is
partially contained in the Address Byte 1 and partially in
bits 7 through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Refer to figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1 0 1 0 S 2 S1 S0 R/ W
SLAVE ADDRESS BYTE
HIGH ORDER ADDRESS
0 0 0 A12 A11 A10 A9 A8
ADDRESS BYTE 1
LOW ORDER ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
7026 FM 06
5

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X24641S8 arduino
X24641
Bus Timing
SCL
SDA IN
tSU:STA
tF
tHIGH
tLOW
tHD:STA tHD:DAT
t SU:DAT
tR
t SU:STO
tAA tDH
t BUF
SDA OUT
Program Cycle Limits
7026 FM 14
Symbol
Parameter
Min.
Typ.(7)
Max.
Units
TWR(8)
Program Cycle Time
5 10 ms
7026 FRM T11
Notes: (7) Typical values are for TA = 25°C and nominal supply voltage (5V).
(8) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the nonvolatile write operation.
The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal
erase/program cycle. During the program cycle, the X24641 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slave address.
Bus Timing
SCL
SDA
8th BIT
WORD n
ACK
ST OP
CONDITION
t WR
START
CONDITION
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
80
60
RMIN
=
VCC MAX
IOL MIN
=1.8K
RMAX
=
tR
CBUS
MAX.
RESISTANCE
40
20 MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
7026 FM 16
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
7026 FM 15
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance 7026 FM 17
11

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