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PDF X24026 Data sheet ( Hoja de datos )

Número de pieza X24026
Descripción Serial E2PROM
Fabricantes Xicor 
Logotipo Xicor Logotipo



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No Preview Available ! X24026 Hoja de datos, Descripción, Manual

ISO 7816 Compatible
2K
X24026
256 x 8 Bit
Serial E2PROM
FEATURES
• 2.7V to 5.5V Power Supply
• Low Power CMOS
—Active Current Less Than 1mA
—Standby Current Less Than 50µA
• Internally Organized 256 x 8
• Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
• 2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
• Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection > 2KV
DESCRIPTION
The X24026 is a CMOS 2048 bit serial E2PROM, inter-
nally organized 256 x 8. The X24026 features a serial
interface and software protocol allowing operation on a
simple two wire bus.
Xicor E2PROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years. Available in DICE form with ISO
7816 compatible pinout.
FUNCTIONAL DIAGRAM
VCC
VSS
SDA
SCL
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
START CYCLE
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
H.V. GENERATION
TIMING
& CONTROL
E2 PROM
64 X 32
R/W
DOUT
ACK
PIN
YDEC
8
CK DATA REGISTER DOUT
7020 FRM 01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7020-1.2 2/24/97 T1/C0/D2 SH
1 Characteristics subject to change without notice

1 page




X24026 pdf
X24026
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24026 this is fixed as 1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
1 0 1 0 0 0 0 R/W
RESERVE
ADDRESS
BITS
7020 FRM 06
The next three significant bits are reserved address bits.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operations is selected.
Figure 5. Byte Write
Following the start condition, the X24026 monitors the
SDA bus comparing the slave address being transmitted
with its slave address. Upon a correct compare the
X24026 outputs an acknowledge on the SDA line.
Depending on the state of the R/W bit, the X24026 will
execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24026 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24026 responds with an acknowledge, and
awaits the next eight bits of data, again responding with
an acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24026
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24026
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
S
T
BUS ACTIVITY: A
MASTER
R
T
SLAVE
ADDRESS
WORD
ADDRESS
SDA LINE
S
BUS ACTIVITY:
X24026
AA
CC
KK
DATA
S
T
O
P
P
A
C
K
7020 FRM 07
Figure 6. Page Write
S
T
BUS ACTIVITY: A
MASTER
R
T
SDA LINE
S
BUS ACTIVITY:
X24026
SLAVE
ADDRESS
WORD
ADDRESS (n)
AA
CC
KK
DATA n
DATA n+1
AA
CC
KK
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
DATA n+3
S
T
O
P
P
A
C
K
7020 FRM 08
5

5 Page





X24026 arduino
X24026
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
tWR(6)
Write Cycle Time
5 10 ms
7020 FRM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
8th BIT
ACK
WORD n
tWR
STOP
CONDITION
START
CONDITION
X24026
ADDRESS
7020 FRM 15
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
120
100
80
60
40
RMIN
= VCC MAX
IOL MIN
tR
RMAX
=
CBUS
MAX.
RESISTANCE
=1.8K
20 MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
7020 FRM 16
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
11

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