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PDF XCR3256XL Data sheet ( Hoja de datos )
| Número de pieza | XCR3256XL | |
| Descripción | 256 Macrocell CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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R XCR3256XL 256 Macrocell CPLD
DS013 (v1.2) May 3, 2000
0 14 Preliminary Product Specification
Features
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 140 MHz
• 256 macrocells with 6,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (116 user I/O pins)
- 208-pin PQFP (160 user I/O)
- 280-ball CS BGA (160 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five metal layer re-
programmable process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per logic block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per logic block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V industrial grade voltage range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate
implementation allows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to Figure 1 and Table 1 showing the ICC vs. Fre-
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25°C).
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
TIN Input buffer delay
TFIN Fast input buffer delay
TGCK
Global clock buffer delay
TOUT
Output buffer delay
TEN Output buffer enable/disable delay
Internal Register and Combinatorial Delays
TLDI Latch transparent delay
TSUI
Register setup time
THI Register hold time
TECSU
Register clock enable setup time
TECHO Register clock enable hold time
TCOI
Register clock to output delay
TAOI Register async. S/R to output delay
TRAI
Register async. recovery
TLOGI1 Internal logic delay (single p-term)
TLOGI2 Internal logic delay (PLA OR term)
Feedback Delays
TF ZIA delay
Time Adders
TLOGI3
TUDA
TSLEW
Fold-back NAND delay
Universal delay
Slew rate limited delay
XCR3256XL 256 Macrocell CPLD
-7
Min. Max.
-10
Min. Max.
-12
Min. Max.
Unit
- 2.5 - 3.3 - 4.0 ns
- 2.2 - 2.8 - 3.3 ns
- 1.0 - 1.3 - 1.5 ns
- 2.5 - 2.8 - 3.3 ns
- 4.5 - 5.2 - 6.0 ns
- 1.3 - 1.6 - 2.0 ns
0.8 - 1.0 - 1.2 - ns
4.0 - 5.5 - 6.7 - ns
2.0 - 2.5 - 3.0 - ns
3.0 - 4.5 - 5.5 - ns
- 1.0 - 1.3 - 1.6 ns
- 2.0 - 2.0 - 2.2 ns
- 5.0 - 7.0 - 8.0 ns
- 2.0 - 2.5 - 3.0 ns
- 2.5 - 3.5 - 4.2 ns
- 2.8 - 3.7 - 4.4 ns
- 6.0 - 8.0 - 9.5 ns
- 2.0 - 2.5 - 3.0 ns
- 4.0 - 5.0 - 6.0 ns
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet XCR3256XL.PDF ] | |
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