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PDF XCR3064XL-10PC44C Data sheet ( Hoja de datos )

Número de pieza XCR3064XL-10PC44C
Descripción XCR3064XL 64 Macrocell CPLD
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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0
R XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002
0 14 Product Specification
Features
• Lowest power 64 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin PLCC (36 user I/O pins)
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25°C).
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0 20 40 60 80 100 120 140
Frequency (MHz)
DS017_01_102401
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140
Typical ICC (mA)
0
0.2 1.0 2.0 3.9 7.6 11.3 14.8 18.5 22.1 25.6
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1

1 page




XCR3064XL-10PC44C pdf
R
Switching Characteristics
VCC
S1
R1
VIN
R2
VOUT
C1
S2
XCR3064XL 64 Macrocell CPLD
Component
R1
R2
C1
Values
390
390
35 pF
Measurement
S1
S2
TPOE (High)
Open
Closed
TPOE (Low)
Closed
Open
TP
Closed
Closed
Note: For TPOD, C1 = 5 pF. Delay measured at
output level of VOL + 300 mV, VOH 300 mV.
Figure 3: AC Load Circuit
DS017_03_102401
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
1 2 4 8 16
Number of Adjacent Outputs Switching
DS017_04_042800
Figure 4: Derating Curve for TPD2
+3.0V
90%
10%
0V
TR
1.5 ns
TL
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 5: Voltage Waveform
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
5

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