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PDF XCR3032XL-7CS48C Data sheet ( Hoja de datos )

Número de pieza XCR3032XL-7CS48C
Descripción XCR3032XL 32 Macrocell CPLD
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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0
R XCR3032XL 32 Macrocell CPLD
DS023 (v1.5) January 8, 2002
0 14 Preliminary Product Specification
Features
• Lowest power 32 macrocell CPLD
• 5.0 ns pin-to-pin logic delays
• System frequencies up to 200 MHz
• 32 macrocells with 750 usable gates
• Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
01
Typical ICC (mA)
0.02 0.13
5
0.54
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
20
15
10
5
0
0 20 40 60 80 100 120 140 160 180 200
Frequency (MHz)
DS023_01_080101
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
10 20
1.06 2.09
50 100 200
5.2 10.26 20.3
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1

1 page




XCR3032XL-7CS48C pdf
R
Switching Characteristics
VCC
S1
R1
VIN
R2
VOUT
C1
S2
XCR3032XL 32 Macrocell CPLD
Component
R1
R2
C1
Values
390
390
35 pF
Measurement
S1
S2
TPOE (High)
TPOE (Low)
TP
Open
Closed
Closed
Closed
Open
Closed
Note: For TPOD, C1 = 5 pF. Delay measured at
output level of VOL + 300 mV, VOH 300 mV.
Figure 3: AC Load Circuit
DS023_03_102401
4.5
4.0
3.5
3.0
1 2 4 8 16
Outputs
DS023_05_061101
Figure 4: Derating Curve for TPD2
+3.0V
90%
10%
0V
TR
1.5 ns
TL
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS023_06_042800
Figure 5: Voltage Waveform
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5

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