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PDF XCR22LV10-10VO24C Data sheet ( Hoja de datos )

Número de pieza XCR22LV10-10VO24C
Descripción TotalCMOS/ Universal PLD Device
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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0
R XCR22LV10: 3V Zero Power,
TotalCMOS, Universal PLD Device
DS047 (v1.1) February 10, 2000
0 0* Product Specification
Features
• Industry's first TotalCMOS™ SPLD - both CMOS
design and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and high speed
- Static current of less than 45 µA
- Dynamic current substantially below that of
competing devices
- Pin-to-pin delay of only 10 ns
• True Zero Power device with no turbo bits or power
down schemes
• Function/JEDEC map compatible with Bipolar,
UVCMOS, EECMOS 22V10s
• Multiple packaging options featuring PCB-friendly
flow-through pinouts (SOL and TSSOP)
- 24-pin TSOIC–uses 93% less in-system space than
a 28-pin PLCC
- 24-pin SOIC
- 28-pin PLCC with standard JEDEC pinout
• Available in commercial and industrial operating ranges
• Supports mixed voltage systems—5V tolerant I/Os
• Advanced 0.5µ E2CMOS process
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Varied product term distribution with up to 16 product
terms per output for complex functions
• Programmable output polarity
• Synchronous preset/asynchronous reset capability
• Security bit prevents unauthorized access
• Electronic signature for identification
• Design entry and verification using industry standard
CAE tools
• Reprogrammable using industry standard device
programmers
Description
The XCR22LV10 is the first SPLD to combine high perfor-
mance with low power, without the need for "turbo bits" or
other power down schemes. To achieve this, Xilinx has
used their FZP design technique, which replaces conven-
tional sense amplifier methods for implementing product
terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates.
This results in the combination of low power and high
speed that has previously been unattainable in the PLD
arena. For 5V operation, Xilinx offers the XCR22V10 that
offers high speed and low power in a 5V implementation.
The XCR22LV10 uses the familiar AND/OR logic array
structure, which allows direct implementation of
sum-of-products equations. This device has a programma-
ble AND array which drives a fixed OR array. The OR sum
of products feeds an "Output Macro Cell" (OMC), which can
be individually configured as a dedicated input, a combina-
torial output, or a registered output with internal feedback.
Functional Description
The XCR22LV10 implements logic functions as
sum-of-products expressions in a programmable-
AND/fixed-OR logic array. User-defined functions are cre-
ated by programming the connections of input signals into
the array. User-configurable output structures in the form of
I/O macrocells further increase logic flexibility (Figure 1).
DS047 (v1.1) February 10, 2000
www.xilinx.com
1-800-255-7778
1

1 page




XCR22LV10-10VO24C pdf
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
R
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled by the
global preset and clear terms. When the synchronous pre-
set term is satisfied, the Q output of the register will be set
High at the next rising edge of the clock input. Satisfying the
asynchronous clear term will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Program/Erase Cycles
The XCR22LV10 is 100% testable, erases/programs in
seconds, and guarantees 1000 program/erase erase
cycles.
Output Polarity
Each macrocell can be configured to implement active High
or active Low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bidi-
rectional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically FALSE and
the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a regis-
tered function (S1=0) (Figure 4a or Figure 4b), the feed-
back signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combi-
natorial function (S1=1) (Figure 4c or Figure 4d), the feed-
back signal is taken from the I/O pin. In this case, the pin
can be used as a dedicated input, a dedicated output, or a
bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a
reset condition and the Q output will be low. The actual out-
put of the XCR22LV10 will depend on the programmed out-
put polarity. The VCC rise must be monotonic.
Design Security
The XCR22LV10 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set, it is impossible to
verify (read) or program the XCR22LV10 until the entire
device has first been erased with the bulk-erase function.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS SPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer SPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must accept low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR22LV10 TotalCMOS SPLD.
Table 1: Typical ICC vs. Frequency @ VCC = 3.3V, 25°C
Frequency (MHz)
1
10
20
30
40
50
60
70
80
90
100
110
120
130
Tupical ICC (mA)
0.2
1.5
3.0
4.5
6.0
7.4
8.9
10.4
11.8
13.2
14.5
15.8
17.0
18.2
5
www.xilinx.com
DS047 (v1.1) February 10, 2000
1-800-255-7778

5 Page





XCR22LV10-10VO24C arduino
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Test Load Circuit
VCC
+3.3V S1
C1 C2
INPUTS
I0 F0
DUT
In Fn
CK OE
GND
R1
R2 CL
NOTE:
C1 and C2 are to bypass VCC to GND.
R1 = 300, R2 = 300, CL = 35pF.
SP00478
Thevenin Equivalent
VL = 1.65V
150
DUT OUTPUT
35 pF
Voltage Waveform
+3.0V
90%
0V
1.5ns
tR tF
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
10%
1.5ns
SP00368
R
11
www.xilinx.com
DS047 (v1.1) February 10, 2000
1-800-255-7778

11 Page







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