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PDF XCB56364PV100 Data sheet ( Hoja de datos )
| Número de pieza | XCB56364PV100 | |
| Descripción | 24-Bit Audio Digital Signal Processor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
Advance Information
DSP56364/D
Rev. 3.2, 08/2003
24-Bit Audio Digital
Signal Processor
Topic
Page
Overview ..................................... i
Features .................................... ii
Signal/Connection
Descriptions .......................1-1
Specifications ..........................2-1
Packaging ...............................3-1
Design Considerations ...........4-1
Ordering Information ...............5-1
IBIS Model ............................. A-1
Overview
The DSP56364 supports digital audio applications requiring sound field processing,
acoustic equalization, and other digital audio algorithms. The DSP56364 uses the
high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing
capability of the Motorola Symphony™ DSP family, as shown in Figure 1. This
design provides a two-fold performance increase over Motorola’s popular
Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction
cache, and direct memory access (DMA). The DSP56364 offers 100 million
instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
Used to indicate a signal that is active when pulled low (For
example, the RESET pin is active when low.)
“asserted”
Means that a high true (active high) signal is high or that a low
true (active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low
true (active low) signal is high
Examples:
Signal/
Symbol
Logic State Signal State Voltage*
PIN
True
Asserted
VIL / VOL
PIN
False
Deasserted
VIH / VOH
PIN
True
Asserted
VIH / VOH
PIN
False
Deasserted
VIL / VOL
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product
specifications.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IMOTOROLA
DSP56364 Advance Information
1
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
1.1 SIGNAL GROUPINGS
The input and output signals of the DSP56364 are organized into functional groups, which are listed in
Table 1-1 and illustrated in Figure 1-1.
The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
Table 1-1 DSP56364 Functional Signal Groupings
Functional Group
Number of
Signals
Detailed
Description
Power (VCC)
Ground (GND)
18 Table 1-2
14 Table 1-3
Clock and PLL
3 Table 1-4
Address bus
18 Table 1-5
Data bus
Bus control
Port A1 8 Table 1-6
6 Table 1-7
Interrupt and mode control
4 Table 1-8
General Purpose I/O
Port B2
4 Table 1-12
SHI 5 Table 1-9
ESAI
Port C3
12 Table 1-10
JTAG/OnCE Port
4 Table 1-11
Notes: 1. Port A is the external memory interface port, including the external address bus, data bus, and control
signals.
2. Port B signals are the GPIO signals.
3. Port C signals are the ESAI port signals multiplexed with the GPIO signals.
MOTOROLA
DSP56364 Advance Information
For More Information On This Product,
Go to: www.freescale.com
1-1
5 Page 
Freescale Semiconductor, Inc.
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
1.5.3
External Bus Control
Table 1-7 External Bus Control Signals
Signal Name Type
AA0–AA1/
RAS0–RAS1
Output
CAS
Output
RD Output
WR Output
TA Input
State
during
Reset
Signal Description
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Ignored
Input
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as RAS, these signals can be used as RAS for DRAM interface.
These signals are tri-statable outputs with programmable polarity. These
signals are tri-stated during hardware reset and when the DSP is in the
stop or wait low-power standby mode.
Column Address Strobe— CAS is an active-low output used by DRAM
to strobe the column address. This signal is tri-stated during hardware
reset and when the DSP is in the stop or wait low-power standby mode.
Read Enable—RD is an active-low output that is asserted to read exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
Write Enable— WR is an active-low output that is asserted to write exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
Transfer Acknowledge—If there is no external bus activity, the TA input
is ignored. The TA input is a data transfer acknowledge (DTACK) function
that can extend an external bus cycle indefinitely. Any number of wait
states (1, 2. . .infinity) may be added to the wait states inserted by the
BCR by keeping TA deasserted. In typical operation, TA is deasserted at
the start of a bus cycle, is asserted to enable completion of the bus cycle,
and is deasserted before the next bus cycle. The current bus cycle com-
pletes one clock period after TA is asserted synchronous to the internal
system clock. The number of wait states is determined by the TA input or
by the bus control register (BCR), whichever is longer. The BCR can be
used to set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit
in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
MOTOROLA
DSP56364 Advance Information
For More Information On This Product,
Go to: www.freescale.com
1-7
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