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Número de pieza XC9572-15PC84I
Descripción XC9572 In-System Programmable CPLD
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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1
® XC9572 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
1 1* Product Specification
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 100-pin TQFP packages
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9572 device.
200
(125)
100
(65)
High Performance
Low Power
(160)
(100)
0 50 100
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XC9572
December 4, 1998 (Version 3.0)
1

1 page




XC9572-15PC84I pdf
XC9572 In-System Programmable CPLD
Internal Timing Parameters
Symbol
Parameter
XC9572-7 XC9572-10
Min Max Min Max
Buffer Delays
tIN Input buffer delay
tGCK
GCK buffer delay
tGSR
GSR buffer delay
tGTS
GTS buffer delay
tOUT
Output buffer delay
tEN Output buffer enable/disable delay
Product Term Control Delays
tPTCK
Product term clock delay
tPTSR
Product term set/reset delay
tPTTS
Product term 3-state delay
Internal Register and Combinatorial delays
tPDI Combinatorial logic propagation delay
tSUI Register setup time
tHI Register hold time
tCOI Register clock to output valid time
tAOI Register async. S/R to output delay
tRAI Register async. S/R recovery before clock
tLOGI
Internal logic delay
tLOGILP Internal low power logic delay
Feedback Delays
tF FastCONNECT matrix feedback delay
tLF Function Block local feeback delay
Time Adders
tPTA3
tSLEW
Incremental Product Term Allocator delay
Slew-rate limited delay
1.5
3.0
7.5
2.5 3.5
1.5 2.5
4.5 6.0
5.5 6.0
2.5 3.0
0.0 0.0
3.0 3.0
2.0 2.5
4.5 3.5
0.5 1.0
2.5
3.5
0.5 0.5
6.5 7.0
10.0
2.0 2.5
10.0 11.0
8.0 9.5
4.0 3.5
1.0 1.0
4.0 4.5
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
XC9572-15
Units
Min Max
4.5
3.0
7.5
11.0
4.5
0.0
ns
ns
ns
ns
ns
ns
2.5 ns
3.0 ns
5.0 ns
3.5
4.5
10.0
3.0
0.5
8.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
11.0 ns
3.5 ns
1.0 ns
5.0 ns
December 4, 1998 (Version 3.0)
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