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PDF XC9536-10VQ44C Data sheet ( Hoja de datos )

Número de pieza XC9536-10VQ44C
Descripción XC9536 In-System Programmable CPLD
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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9
®
1
XC9536 In-System Programmable
CPLD
December 4, 1998 (Version 5.0)
1 1* Product Specification
Features
• 5 ns pin-to-pin logic delays on all pins
• fCNT to 100 MHz
• 36 macrocells with 800 usable gates
• Up to 34 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
High Performance
(50)
Low Power
(30)
(83)
(50)
0 50 100
Clock Frequency (MHz)
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
December 4, 1998 (Version 5.0)
1

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XC9536-10VQ44C pdf
Device Output
VTEST
R1
R2
XC9536 In-System Programmable CPLD
Output Type
VCCIO
5.0 V
VTEST
5.0 V
R1
160
R2
120
CL
35 pF
3.3 V
3.3 V
260
360
35 pF
CL X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Units
Min Max Min Max Min Max Min Max Min Max
Buffer Delays
tIN Input buffer delay
tGCK GCK buffer delay
tGSR GSR buffer delay
tGTS GTS buffer delay
tOUT Output buffer delay
tEN Output buffer enable/disable delay
Product Term Control Delays
1.5 1.5 2.5 3.5 4.5 ns
1.5 1.5 1.5 2.5 3.0 ns
4.0 4.0 4.5 6.0 7.5 ns
5.0 5.0 5.5 6.0 11.0 ns
2.0 2.0 2.5 3.0 4.5 ns
0.0 0.0 0.0 0.0 0.0 ns
tPTCK Product term clock delay
tPTSR Product term set/reset delay
tPTTS Product term 3-state delay
Internal Register and Combinatorial delays
3.0 3.0 3.0 3.0 2.5 ns
1.0 1.0 2.0 2.5 3.0 ns
5.5 5.5 4.5 3.5 5.0 ns
tPDI Combinatorial logic propagation delay
0.5 1.5 0.5 1.0 3.0 ns
tSUI Register setup time
2.5 2.5 1.5 2.5 3.5
ns
tHI Register hold time
1.0 1.0 3.0 3.5 4.5
ns
tCOI Register clock to output valid time
0.5 0.5 0.5 0.5 0.5 ns
tAOI Register async. S/R to output delay
6.0 6.0 6.5 7.0 8.0 ns
tRAI Register async. S/R recovery before clock 5.0 5.0 7.5 10.0 10.0
ns
tLOGI Internal logic delay
1.0 1.0 2.0 2.5 3.0 ns
tLOGILP Internal low power logic delay
9.0 9.0 10.0 11.0 11.5 ns
Feedback Delays
tF FastCONNECT matrix feeback delay
Time Adders
6.0 6.0 8.0 9.5 11.0 ns
tPTA3 Incremental Product Term Allocator delay 0.8 0.8 1.0 1.0 1.0 ns
tSLEW Slew-rate limited delay
3.5 3.5 4.0 4.5 5.0 ns
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 5.0)
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