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PDF XC95288XL Data sheet ( Hoja de datos )
| Número de pieza | XC95288XL | |
| Descripción | High Performance CPLD | |
| Fabricantes | Xilinx | |
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R XC95288XL High Performance
CPLD
DS055 (v2.1 April 3, 2007
05
Features
• 6 ns pin-to-pin logic delays
• System frequency up to 208 MHz
• 288 macrocells with 6,400 usable gates
• Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
Product Specification
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
© 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS055 (v2.1 April 3, 2007
Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R
AC Characteristics
Symbol
TPD
TSU
TH
TCO
fSYSTEM
TPSU
TPH
TPCO
TOE
TOD
TPOE
TPOD
TAO
TPAO
TWLH
TAPRPW
TPLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
P-term S/R to output valid
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width
(High or Low)
P-term clock pulse width (High or Low)
XC95288XL High Performance CPLD
XC95288XL-6
Min Max
- 6.0
4.0 -
0-
- 3.8
- 208.3
1.0 -
2.6 -
- 6.8
- 4.5
- 4.5
- 8.4
- 8.4
- 10.8
- 11.8
2.4 -
6.0 -
XC95288XL-7
Min Max
- 7.5
4.8 -
0-
- 4.5
- 125.0
1.6 -
3.2 -
- 7.7
- 5.0
- 5.0
- 9.5
- 9.5
- 12.0
- 12.6
4.0 -
6.5 -
XC95288XL-10
Min Max
- 10.0
6.5 -
0-
- 5.8
- 100.0
2.1 -
4.4 -
- 10.2
- 7.0
- 7.0
- 11.0
- 11.0
- 14.5
- 15.3
4.5 -
7.0 -
Units
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0 - 6.5 - 7.0 - ns
Device Output
VTEST
R1
R2
Output Type VCCIO
3.3V
VTEST
3.3V
2.5V
2.5V
CL
Figure 3: AC Load Circuit
R1
320 Ω
250 Ω
R2
360 Ω
660 Ω
CL
35 pF
35 pF
DS058_03_081500
DS055 (v2.1 April 3, 2007
Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R XC95288XL High Performance CPLD
XC95288XL Global, JTAG and Power Pins(1)
Pin Type
TQ144
PQ208
BG256
FG256
CS280
I/O/GCK1
30
44
T2
M2
R3
I/O/GCK2
32
46
U2
M3
T1
I/O/GCK3
38
55
W4
P5
W2
I/O/GTS1
5
7
C1
D4
D3
I/O/GTS2
6
9
E1
E5
E2
I/O/GTS3
2
3
C2
D3
C2
I/O/GTS4
3
5
D3
E3
C1
I/O/GSR
143
206
A2
C4
C4
TCK
67
98
U16
P12
T15
TDI 63 94 W16 R11 U14
TDO
122
176
B12
A10
D13
TMS
65
96
W17
N12
U15
VCCINT 3.3V
8, 42, 84, 141
11, 59, 124, 153,
204
F1, P2, W5, Y9,
V10, U13, W18,
T20, M19, F20, E17,
B17, B14, A10, C7,
B3, G4
F4, F7, G6, H6, J6,
K6, L7, F8, L8, F9,
L9, F10, L10, G11,
H11, J11, K11
E1, F2, N3, U5, W9,
V9, U12, V16, R17,
M18, G18, D19,
C18, A15, A11, D8,
A4
VCCIO 2.5V/3.3 V 1, 37, 55, 73, 109, 1, 26, 53, 65, 79,
127 92, 105, 132, 157,
172, 181, 184
D4, D6, D11, D15,
D17, F4, F17, K4,
L17, R4, R17, U4,
U6, U10, U15, U17
F3, K4, D5, F6, L6, C3, F1, K1, N4, V2
P6, C7, N9, C10, T6, T10, V14, V18,
F11, L11, P11, D12, P18, K19, G17,
G13, L14
C19, D14, D12, D11,
A7
GND
18, 29, 36, 47, 62,
72, 89, 90, 99,
108, 114, 123,
144
2, 13, 24, 27, 42,
52, 68, 81, 93,
104,1 08, 129,
130, 141, 156,
163, 177, 190,
207
B1, K3, T1, Y5,
W10, Y10, Y14,
V15, U18, R19, K20,
G18, B16, D13, A11,
A6, J9, J10, J11,
J12, K9, K10, K11,
K12, L9, L10, L11,
L12, M9, M10, M11,
M12
A1, A16, C14, T1,
B2, B15, R2, C3,
P3, G7, H7, J7, K7,
G8, H8, J8, K8, G9,
H9, J9, K9, G10,
H10, J10, K10, P14,
R15, T16
E5, F5, G5, H5, J5,
K5, L5, M5, N5, R5,
R6, R7, R8, R9 R10,
R11, R12, R13, R14,
R15, P15, N15,
M15, L15, K15, J15,
H15, G15, F15, E15,
E14, E13, E12, E11,
E10, E9, E8, E7, E6,
P5
No Connects
–
– A1, A19, A20, B19,
B20, C19, W1, W2,
W3, W20, Y1
-
A1, B2, W1, U3,
W19, U17, A19,
C17, A2, B3
Notes:
1. The pin-outs are the same for Pb-free versions of packages.
DS055 (v2.1 April 3, 2007
Product Specification
www.xilinx.com
1-800-255-7778
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet XC95288XL.PDF ] | |
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