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PDF XC9500 Data sheet ( Hoja de datos )
| Número de pieza | XC9500 | |
| Descripción | XC9500 In-System Programmable CPLD Family | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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XC9500 In-System Programmable
CPLD Family
DS063 (v5.1) September 22, 2003
0 0 Product Specification
Features
• High-performance
- 5 ns pin-to-pin logic delays on all pins
- fCNT to 125 MHz
• Large density range
- 36 to 288 macrocells with 800 to 6,400 usable
gates
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
- Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
- Programmable power reduction mode in each
macrocell
- Slew rate control on individual outputs
- User programmable ground pin capability
- Extended pattern security features for design
protection
- High-drive 24 mA outputs
- 3.3V or 5V I/O capability
- Advanced CMOS 5V Fast FLASH™ technology
- Supports parallel programming of multiple XC9500
devices
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in Table 1, logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and asso-
ciated I/O capacity are shown in Table 2. The XC9500 fam-
ily is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.
Table 1: XC9500 Device Family
XC9536
XC9572
XC95108
XC95144
XC95216
Macrocells
36 72 108 144 216
Usable Gates
800
1,600
2,400
3,200
4,800
Registers
36 72 108 144 216
TPD (ns)
5 7.5 7.5 7.5 10
TSU (ns)
3.5 4.5 4.5 4.5 6.0
TCO (ns)
fCNT (MHz)(1)
4.0 4.5 4.5 4.5 6.0
100 125 125 125 111.1
fSYSTEM (MHz)(2) 100 83.3 83.3 83.3 66.7
Notes:
1. fCNT = Operating frequency for 16-bit counters.
2. fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.
XC95288
288
6,400
288
15
8.0
8.0
92.2
56.6
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
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All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in Figure 4, the macrocell register clock
originates from either of three global clocks or a product
XC9500 In-System Programmable CPLD Family
term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
Product Term Set
Product Term Clock
Product Term Reset
Macrocell
S
D/T
R
I/O/GSR
I/O/GCK1
I/O/GCK2
I/O/GCK3
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
Figure 4: Macrocell Clock and Set/Reset Capability
DS063_04_110501
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
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Each output has independent slew rate control. Output
edge rates may be slowed down to reduce system noise
(with an additional time delay of TSLEW) through program-
ming. See Figure 11.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins. By tying strategically located programmable
ground pins to the external ground connection, system
noise generated from large numbers of simultaneous
switching outputs may be reduced.
A control pull-up resistor (typically 10K ohms) is attached to
each device I/O pin to prevent them from floating when the
device is not in normal user operation. This resistor is active
during device programming mode and system power-up. It
is also activated for an erased device. The resistor is deac-
tivated during normal operation.
The output driver is capable of supplying 24 mA output
drive. All output drivers in the device may be configured for
either 5V TTL levels or 3.3V levels by connecting the device
output voltage supply (VCCIO) to a 5V or 3.3V voltage sup-
Output
Voltage
XC9500 In-System Programmable CPLD Family
ply. Figure 12 shows how the XC9500 device can be used in
5V only and mixed 3.3V/5V systems.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design changes depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500 devices
have architectural features that enhance the ability to
accept design changes while maintaining the same pinout.
The XC9500 architecture provides maximum routing within
the Fast CONNECT switch matrix, and incorporates a flexi-
ble Function Block that allows block-wide allocation of avail-
able product terms. This provides a high level of confidence
of maintaining both input and output pin assignments for
unexpected design changes.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework
Output
Voltage
1.5V
0
5V CMOS or
5V
0V
5V TTL or
3.6V
0V
3.3V
3.3V
0V
Standard
TSLEW
Slew-Rate Limited
1.5V
Slew-Rate Limited
TSLEW
Standard
Time
0
(a)
(b)
Figure 11: Output slew-Rate for (a) Rising and (b) Falling Outputs
Time
DS063_11_110501
5V
VCCINT VCCIO
XC9500
IN CPLD OUT
5V TTL
–4V
0V
GND
(a)
5V CMOS or
5V
0V
5V TTL or
3.6V
0V
3.3V
3.3V
0V
5V 3.3V
VCCINT VCCIO
XC9500
IN CPLD OUT
GND
(b)
Figure 12: XC9500 Devices in (a) 5V Systems and (b) Mixed 5V/3.3V Systems
3.3V
3.3V
0V
DS063_12_110501
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet XC9500.PDF ] | |
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