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PDF XC73144-12 Data sheet ( Hoja de datos )

Número de pieza XC73144-12
Descripción 144-Macrocell CMOS EPLD
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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® XC73144
144-Macrocell CMOS EPLD
Product Specifications
Features
• High-Performance EPLD
– 7.5 ns pin-to-pin speed on all fast inputs
– 100 MHz maximum clock frequency
• Advanced Dual-Block architecture
– Four Fast Function Blocks
– Twelve High-Density Function Blocks
• 100% interconnect matrix
• High-Speed arithmetic carry network
– 1 ns ripple-carry delay per bit
– 43 MHz 16-bit accumulators
• 144 Macrocells with programmable I/O architecture
• Up to 132 inputs programmable as direct, latched, or
registered
• All outputs with 24 mA drive
• 3.3 V or 5 V I/O operation
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• Power management options
• Multiple security bits for design protection
• 160-pin plastic quad flat pack and 225-pin ball-grid-
array packages
• 100% PCI compliant
• Programmable slew rate
• Programmable ground control
General Description
The XC73144 is a member of the Xilinx Dual-Block EPLD
family. It consists of four Fast Function Blocks and twelve
High-Density Function Blocks interconnected by a central
Universal Interconnect Matrix (UIM).
The sixteen Function Blocks in the XC73144 are PAL-like
structures, complete with programmable product term
arrays and programmable multilevel Macrocells. Each
Function Block receives 24 inputs, contains nine Macro-
cells configurable for registered or combinatorial logic and
produces nine outputs which feedback to the UIM and
output pins.
The Universal Interconnect Matrix connects the Function
Blocks to each other and to all input pins, providing 100%
connectivity between the Function Blocks. This allows
logic functions to be mapped into the Function Blocks and
interconnected without routing restrictions.
The XC73144 is designed in a 0.8 µ CMOS EPROM tech-
nology.
In addition, the XC73144 includes a programmable power
management feature to specify high-performance or low-
power operation on an individual Macrocell-by-Macrocell
basis. Unused Macrocells are automatically turned off to
minimize power dissipation. Designers can operate
speed-critical paths at maximum performance, while non-
critical paths dissipate less power.
Xilinx development software (XEPLD) supports all mem-
bers of XC7300 family. The designer can create, imple-
ment, and verify digital logic circuits for EPLD devices
using the Xilinx XEPLD Development System. Designs
can be represented as schematics consisting of XEPLD
library components, as behavioral descriptions, or as a
mixture of both. The XEPLD translator automatically per-
forms logic optimization, collapsing, mapping and routing
without user intervention. After compiling the design,
XEPLD translator produces documentation for design
analysis and creates a programming file to configure the
device.
The following lists some of the XEPLD Development Sys-
tem features.
• Familiar design approach similar to TTL and PLD
techniques
• Converts netlist to fuse map in minutes using a 386/
486 PC or workstation platform
• Interfaces to standard third-party CAE schematics,
simulation tools, and behavioral languages
• Timing simulation using Viewsim, OrCAD VST, Mentor,
LMC and other tools compatible with the Xilinx Netlist
Format (XNF)
2-65
This document was created with FrameMaker 4 0 2

1 page




XC73144-12 pdf
XC73144 CMOS EPLD
Fast Function Block (FFB) External AC Characteristics 3
Symbol Parameter
fCF Max count frequency 1, 2
tSUF Fast input setup time before FCLK 1
tHF Fast input hold time after FCLK
tCOF
tPDFO
tPDFU
FCLK to output valid
Fast input to output valid 1, 2
I/O to output valid 1, 2
tCWF
Fast clock pulse width
XC73144-7
(Com Only)
XC73144-10
(Com Only)
XC73144-12
(Com/Ind Only)
XC73144-15
Min Max Min
105.0
100.0
4.0
0
5.5
5.0
0
7.5
13.5
4.0
5.0
Max
8.0
10.0
19.0
Min
80.0
6.0
0
5.5
Max
9.0
12.0
22.0
Min Max Units
66.7 MHz
7.0
0
12.0
ns
ns
ns
15.0
27.0
6.0
ns
ns
ns
High-Density Function Block (FB) External AC Characteristics
Symbol
fC
tSU
tH
tCO
tPSU
tPH
tPCO
tPD
tCW
tPCW
Parameter
Max count frequency 1, 2
I/O setup time before FCLK 1, 2
I/O hold time after FCLK
FCLK to output valid
I/O setup time before p-term clock 2
I/O hold time after p-term clock
P-term clock to output valid
I/O to output valid 1, 2
Fast clock pulse width
P-term clock pulse width
XC73144-7
(Com Only)
XC73144-10
(Com Only)
XC73144-12
(Com/Ind Only)
XC73144-15
Min Max Min Max Min Max Min Max Units
83.3 62.5 55.6 45.5 MHz
12.0 16.0 18.0 22.0 ns
0 0 0 0 ns
7.0 10.0 12.0 15.0 ns
4.0
6.0 7.0
9.0 ns
0 0 0 0 ns
15.0 20.0 23.0 28.0 ns
18.0 25.0 30.0 36.0 ns
4.0
5.0 5.5
6.0 ns
5.0
6.0 7.5
8.5 ns
Preliminary
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
2-69

5 Page





XC73144-12 arduino
XC73144 CMOS EPLD
For a detailed description of the device architecture, see the XC7300 CMOS EPLD Family data sheet, page 2-1
through 2-10.
For a detailed description of the device timing, see pages 2-9, 2-10 and 2-50 through 2-52.
For package physical dimensions and thermal data, see Section 4.
Ordering Information
XC73144 - 7 PQ 160 C
Device Type
Temperature Range
Speed
Speed Options
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay (commercial only)
-7 7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PQ160 160-Pin Plastic Quad Flat Pack
BG225 225-Pin Plastic Ball-Grid-Array
Temperature Options
C Commercial 0oC to 70oC
I Industrial -40oC to 85oC
Number of Pins
Package Type
Component Availability
Pins
44
Type
Plastic Ceramic Plastic
PLCC CLCC PQFP
Code
PC44 WC44 PQ44
-15
XC73144 -12
-10
-7
68
Plastic Ceramic
PLCC CLCC
PC68 WC68
84
Plastic Ceramic
PLCC CLCC
PC84 WC84
100 144
Plastic Ceramic
PQFP PGA
PQ100 PG144
160
Plastic
PQFP
PQ160
CI
CI
C
C
225
Plastic Ceramic
BGA BGA
BG225
CI
CI
C
C
WB225
CI
CI
C
C
C = Commercial = 0° to +70°C I = Industrial = -40° to 85°C
Parenthesis indicate future product plans
X5654
2-75

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