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Descripción Field Programmable Gate Arrays
Fabricantes Xilinx 
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0
R XC5200 Series
Field Programmable Gate Arrays
November 5, 1998 (Version 5.2)
0 7* Product Specification
Features
• Low-cost, register/latch rich, SRAM based
reprogrammable architecture
- 0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRingI/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic
functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution
nets
• Versatile I/O and Packaging
- Innovative VersaRingI/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes
performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies
system timing
- Independent Output Enables for external bussing
- Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
- Over 150 device/package combinations, including
advanced BGA, TQ, and VQ packaging available
• Fully Supported by Xilinx Development System
- Automatic place and route software
- Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
- Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to pro-
grammable logic design. The VersaBlocklogic module,
the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on
popular workstation and PC platforms. Popular design
entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Design-
ers utilizing logic synthesis can use their existing tools to
design with the XC5200 devices.
.
Table 1: XC5200 Field-Programmable Gate Array Family Members
Device
Logic Cells
Max Logic Gates
Typical Gate Range
VersaBlock Array
CLBs
Flip-Flops
I/Os
TBUFs per Longline
XC5202
256
3,000
2,000 - 3,000
8x8
64
256
84
10
XC5204
XC5206
XC5210
XC5215
480
784
1,296
1,936
6,000
10,000
16,000
23,000
4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
10 x 12
14 x 14
18 x 18
22 x 22
120 196 324 484
480
784
1,296
1,936
124 148 196 244
14 16 20 24
7
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XC5215-4PQ100C pdf
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XC5200 Series Field Programmable Gate Arrays
single-length lines, double-length lines, and Longlines all
routed through the GRM. The direct connects, LIM, and
logic-cell feedthrough are contained within each
Versa-Block. Throughout the XC5200 interconnect, an effi-
cient multiplexing scheme, in combination with three layer
metal (TLM), was used to improve the overall efficiency of
silicon usage.
Performance Overview
The XC5200 family has been benchmarked with many
designs running synchronous clock rates beyond 66 MHz.
The performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the intercon-
nect routing. A rough estimate of timing can be made by
assuming 3-6 ns per logic level, which includes direct-con-
nect routing delays, depending on speed grade. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys-
tem designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be recon-
figured dynamically to perform different functions at differ-
ent times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfig-
ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Detailed Functional Description
Configurable Logic Blocks (CLBs)
Figure 4 shows the logic in the XC5200 CLB, which con-
sists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a
D-Type flip-flop or latch with common clock, clock enable,
and clear, but individually selectable clock polarity. Addi-
tional logic features provided in the CLB are:
• An independent 5-input LUT by combining two 4-input
LUTs.
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Individual selection of either a transparent,
level-sensitive latch or a D flip-flop.
• Four 3-state buffers with a shared Output Enable.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
CO
DI
I1
I2
F4
F3
I3 F2 F
I4 F1
F5_MUX
I5 DI
DO
DQ
FD
X
LC1
DO
out
F4
F3
F2 F
F1
DQ
FD
CI CE CK
5-Input Function
X
CLR LC0
Qout
X5710
Figure 5: Two LUTs in Parallel Combined to Create a
5-input Function
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XC5215-4PQ100C arduino
R
XC5200 Series Field Programmable Gate Arrays
to Vcc. The configurable pull-down resistor is an n-channel
transistor that pulls to Ground.
The value of these resistors is 20 kΩ − 100 k. This high
value makes them unsuitable as wired-AND pull-up resis-
tors.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See Table 13 on
page 124 for a list of pins with pull-ups active before and
during configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, simplifying board-level testing. More informa-
tion is provided in “Boundary Scan” on page 98.
Oscillator
XC5200 devices include an internal oscillator. This oscilla-
tor is used to clock the power-on time-out, clear configura-
tion memory, and source CCLK in Master configuration
modes. The oscillator runs at a nominal 12 MHz frequency
that varies with process, Vcc, and temperature. The output
CCLK frequency is selectable as 1 MHz (default), 6 MHz,
or 12 MHz.
The XC5200 oscillator divides the internal 12-MHz clock or
a user clock. The user then has the choice of dividing by 4,
16, 64, or 256 for the “OSC1” output and dividing by 2, 8,
32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out-
put. The division is specified via a “DIVIDEn_BY=x”
attribute on the symbol, where n=1 for OSC1, or n=2 for
OSC2. These frequencies can vary by as much as -50% or
+ 50%.
The OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see Figure 13).
OSCS
OSC1
OSC2
CK_DIV
OSC1
OSC2
5200_14
Figure 13: XC5200 Oscillator Macros
VersaBlock Routing
The General Routing Matrix (GRM) connects to the
Versa-Block via 24 bidirectional ports (M0-M23). Excluding
direct connections, global nets, and 3-statable Longlines,
all VersaBlock inputs and outputs connect to the GRM via
these 24 ports. Four 3-statable unidirectional signals
(TQ0-TQ3) drive out of the VersaBlock directly onto the
horizontal and vertical Longlines. Two horizontal global
nets and two vertical global nets connect directly to every
CLB clock pin; they can connect to other CLB inputs via the
GRM. Each CLB also has four unidirectional direct con-
nects to each of its four neighboring CLBs. These direct
connects can also feed directly back to the CLB (see
Figure 14).
In addition, each CLB has 16 direct inputs, four direct con-
nections from each of the neighboring CLBs. These direct
connections provide high-speed local routing that
bypasses the GRM.
Local Interconnect Matrix
The Local Interconnect Matrix (LIM) is built from input and
output multiplexers. The 13 CLB outputs (12 LC outputs
plus a Vcc/GND signal) connect to the eight VersaBlock
outputs via the output multiplexers, which consist of eight
fully populated 13-to-1 multiplexers. Of the eight
VersaBlock outputs, four signals drive each neighboring
CLB directly, and provide a direct feedback path to the input
multiplexers. The four remaining multiplexer outputs can
drive the GRM through four TBUFs (TQ0-TQ3). All eight
multiplexer outputs can connect to the GRM through the
bidirectional M0-M23 signals. All eight signals also connect
to the input multiplexers and are potential inputs to that
CLB.
7
November 5, 1998 (Version 5.2)
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