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PDF XC4005E Data sheet ( Hoja de datos )

Número de pieza XC4005E
Descripción XC4000E and XC4000X Series Field Programmable Gate Arrays
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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Product Obsolete or Under Obsolescence
0
R XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6)
0 0* Product Specification
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx web site at
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
• System featured Field-Programmable Gate Arrays
- SelectRAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -2 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 80 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
• Configured by Loading Binary File
- Unlimited re-programmability
• Read Back Capability
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 µm SRAM process for XC4000XL
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• Four Additional Address Bits in Master Parallel
Configuration Mode
0
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
6
May 14, 1999 (Version 1.6)
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XC4005E pdf
Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Detailed Functional Description
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
the user’s logic.
• IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
• Wide edge decoders are available around the periphery
of each device.
• An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function gener-
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expand-
able-identity comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be configured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplifies routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F’ and G’ functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, H0). The third input must come from
outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
• any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
• any single function of five variables
• any function of four variables together with some
functions of six variables
• some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
May 14, 1999 (Version 1.6)
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XC4005E arduino
Product Obsolete or Under Obsolescence
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 3.
Figure 6 shows a simple model of an XC4000 Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 6. See Figure 7 on page 16 for a block diagram of a
CLB configured in this mode.
WE
D
DPRA[3:0]
RAM16X1D Primitive
WE
D
AR[3:0]
AW[3:0]
DQ
DPO (Dual Port Out)
Registered DPO
A[3:0]
G Function Generator
WE
D
AR[3:0]
AW[3:0]
DQ
SPO (Single Port Out)
Registered SPO
WCLK
F Function Generator
X6755
Figure 6: XC4000 Series Dual-Port RAM, Simple
Model
Table 6: Dual-Port Edge-Triggered RAM Signals
RAM Signal CLB Pin
D D0
A[3:0]
F1-F4
DPRA[3:0]
WE
WCLK
SPO
G1-G4
WE
K
F’
DPO
G’
Function
Data In
Read Address for F,
Write Address for F and G
Read Address for G
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-com-
patibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be care-
fully verified to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs.
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
6
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