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PDF XC4004A Data sheet ( Hoja de datos )

Número de pieza XC4004A
Descripción Logic Cell Array Family
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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No Preview Available ! XC4004A Hoja de datos, Descripción, Manual

® XC4000A
Logic Cell Array Family
Product Specifications
Features
Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders (two per edge)
– Hierarchy of interconnect lines
– Internal 3-state bus capability
– Eight global low-skew clock or signal distribution
network
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate (4 modes)
– Programmable input pull-up or pull-down resistors
– 24-mA sink current per output (48 per pair)
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Description
The XC4000A family of FPGAs offers four devices at the low
end of the XC4000 family complexity range. XC4000A
differs from XC4000 in four areas: fewer routing resources,
fewer wide-edge decoders, higher output sink current, and
improved output slew-rate control.
The XC4000 routing structure is optimized for smaller
designs, naturally requiring fewer routing resources. The
XC4000A devices have four Longlines and four single-
length lines per row and column, while the XC4000
devices have six Longlines and eight single-length lines
per row and column. This results in a smaller chip area
and lower cost per device.
XC4000A has two wide-edge decoders on every device
edge, while the XC4000 has four. All other wide-decoder
features are identical in XC4000 and XC4000A.
XC4000A outputs are specified at 24 mA, sink current,
while XC4000 outputs are specified at 12 mA. The source
current is the same 4 mA for both families.
The XC4000A family offers a more sophisticated output
slew-rate control structure with four configurable options
for each individual output driver: fast, medium fast, me-
dium slow, and slow. Slew-rate control can alleviate
ground-bounce problems when multiple outputs switch
simultaneously, and it can reduce or eliminate crosstalk
and transmission-line effects on printed circuit boards.
Note that the XC4003 and XC4005 devices are available in
both flavors, the lower-priced XC4003A/XC4005A with re-
duced routing, and the higher-priced XC4003/XC4005 with
more abundant routing resources. The XC4000A devices
are intended for less demanding and more structured
designs, and the XC4000 devices for more random designs
requiring additional routing resources.
The equivalent devices are pin-compatible and are avail-
able in identical packages, but they are not bitstream
compatible. In order to move from a XC4000A to a XC4000,
or vice versa, the design must be recompiled.
Table 1. The XC4000A Family of Field-Programmable Gate Arrays
Device
XC4002A
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
2,000
8x8
64
256
24
2,048
64
XC4003A
3,000
10 x 10
100
360
30
3,200
80
XC4004A
4,000
12 x 12
144
480
36
4,608
96
XC4005A
5,000
14 x 14
196
616
42
6,272
112
2-71

1 page




XC4004A pdf
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy
between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
Description
Global Clock to Output (fast)
Global Clock to Output (slew limited)
Input Set-up Time, using IFF (no delay)
Input Hold time, using IFF (no delay)
Input Set-up Time, using IFF (with delay)
Input Hold Time, using IFF (with delay)
Speed Grade
Symbol Device
TICKOF
(Max)
TICKO
(Max)
TPSUF
(Min)
TPHF
(Min)
TPSU
(Min)
TPH
(Min)
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
-6
14.9
15.1
15.3
15.5
19.9
20.1
20.3
20.5
2.6
2.4
2.2
2.0
4.9
5.1
5.3
5.5
21.8
21.5
21.2
21.0
0
0
0
0
-5
12.2
12.5
12.8
13.0
15.2
15.5
15.8
16.0
2.3
2.0
1.7
1.5
3.7
4.0
4.3
4.5
18.8
18.5
18.2
18.0
0
0
0
0
-4
Units
ns
11.6 ns
ns
12.0 ns
ns
14.6 ns
ns
15.0 ns
ns
1.6 ns
ns
1.2 ns
ns
4.0 ns
ns
4.5 ns
ns
12.0 ns
ns
12.0 ns
ns
0 ns
ns
0 ns
Input
Set-Up
&
Hold
Time
IFF
TPG
Global Clock-to-Output Delay
OFF
X3192
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture). When testing fast out-
puts, only one output switches. When testing slew-rate
limited outputs, half the number of outputs on one side of the
device are switching. These parameter values are tested
and guaranteed for worst-case conditions of supply voltage
and temperature, and also with the most unfavorable clock
polarity choice.
TPDLI for -4 Speed Grade
Pad to I1, I2
XC4003A 17.6 ns
via transparent
latch, with delay XC4005A 17.9 ns
PRELIMINARY
See page 2-76
TPICKD for -4 Speed Grade
Input set-up time XC4003A 15.6 ns
pad to clock (IK)
with delay
XC4005A 15.9 ns
PRELIMINARY
X6091
2-75

5 Page





XC4004A arduino
XC4002A Pinouts
Pin Bound
Description PC84 PQ100 VQ100 PG120 Scan
VCC
2 92 89 G3 –
I/O (A8)
3 93 90 G1 26
I/O (A9)
4 94 91 F1 29
– – 95* 92* E1*
– – 96* 93* F2*
I/O (A10)
5 97 94 F3 32
I/O (A11)
6 98 95 D1 35
– – – – E2*
I/O (A12)
7 99 96 C1 38
I/O (A13)
8 100 97 D2 41
– – – – E3*
– – – – B1*
I/O (A14)
9 1 98 C2 44
SGCK1 (A15, I/O) 10 2 99 D3 47
VCC
11 3 100 C3 –
GND
12 4
1 C4 –
PGCK1 (A16, I/O) 13 5
2 B2 50
I/O (A17)
14 6
3 B3 53
– – – – A1*
– – – – A2*
I/O (TDI)
15 7
4 C5 56
I/O (TCK)
16 8
5 B4 59
– – – – A3*
I/O (TMS)
17 9
6 B5 62
I/O 18 10 7 A4 65
– – – – C6*
– – 11* 8* A5*
I/O 19 12 9 B6 68
I/O 20 13 10 A6 71
GND
21 14 11 B7 –
VCC
22 15 12 C7 –
I/O 23 16 13 A7 74
I/O 24 17 14 A8 77
– – 18* 15* A9*
– – – – B8*
I/O 25 19 16 C8 80
I/O 26 20 17 A10 83
I/O 27 21 18 B9 86
I/O – 22 19 A11 89
– – – – B10*
Pin
Description
I/O
SGCK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O (LDC)
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
Bound
PC84 PQ100 VQ100 PG120 Scan
28 23 20 C9 92
29 24 21 A12 95
30 25 22 B11 98
31 26 23 C10 –
32 27 24 C11 101†
33 28 25 D11 –
34 29 26 B12 102†
35 30 27 C12 103
36 31 28 A13 106
– – – B13*
– – – E11*
– 32 29 D12 109
37 33 30 C13 112
38 34 31 E12 115
39 35 32 D13 118
– 36* 33* F11*
– 37* 34* E13*
40 38 35 F12 121
41 39 36 F13 124
42 40 37 G12 –
43 41 38 G11 –
44 42 39 G13 127
45 43 40 H13 130
– 44* 41* J13*
– 45* 42* H12*
46 46 43 H11 133
47 47 44 K13 136
48 48 45 J12 139
49 49 46 L13 142
– – – K12*
– – – J11*
50 50 47 M13 145
51 51 48 L12 148
52 52 49 K11 –
53 53 50 L11 –
54 54 51 L10 –
55 55 52 M12 –
56 56 53 M11 151
57 57 54 N13 154
– – – N12*
Pin Bound
Description PC84 PQ100 VQ100 PG120 Scan
– – – L9 –
I/O (D6)
58 58 55 M10 157
I/O – 59 56 N11 160
I/O (D5)
59 60 57 M9 163
I/O (CSO)
60 61 58 N10 166
– – 62* 59* L8*
– – 63* 60* N9*
I/O (D4)
61 64 61 M8 169
I/O 62 65 62 N8 172
VCC
63 66 63 M7 –
GND
64 67 64 L7 –
I/O (D3)
65 68 65 N7 175
I/O (RS)
66 69 66 N6 178
– – 70* 67* N5*
– – – – M6*
I/O (D2)
67 71 68 L6 181
I/O 68 72 69 N4 184
I/O (D1)
69 73 70 M5 187
I/O (RCLK-BUSY/RDY) 70 74 71 N3 190
– – – – M4*
– – – – L5*
I/O (D0, DIN) 71 75 72 N2 193
SGCK4 (DOUT, I/O) 72 76 73 M3 196
CCLK
73 77 74 L4 –
VCC
74 78 75 L3 –
O (TDO)
75 79 76 M2 –
GND
76 80 77 K3 –
I/O (A0, WS) 77 81 78 L2 2
PGCK4 (I/O,A1) 78 82 79 N1 5
– – – – M1*
– – – – J3*
I/O (CS1, A2) 79 83 80 K2 8
I/O (A3)
80 84 81 L1 11
I/O (A4)
81 85 82 J2 14
I/O (A5)
82 86 83 K1 17
– – 87* 84* H3*
– – 88* 85* J1*
I/O (A6)
83 89 86 H2 20
I/O (A7)
84 90 87 H1 23
GND
1 91 88 G2 –
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 199 = BSCANT.UPD
2-81
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